SWRZ131B September   2022  – June 2024 CC1354R10

 

  1.   1
  2.   Trademarks
  3. 1Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Advisories
    1.     Radio_01
    2. 3.1 Radio_05
    3.     Power_03
    4.     PKA_01
    5.     PKA_02
    6.     I2C_01
    7.     I2S_01
    8.     CPU_Sys_01
    9. 3.2 CPU_04
    10.     Sys_01
    11.     SYSCTRL_01
    12.     IOC_01
    13.     ADC_02
    14.     Flash_02
  6. 4Revision History

SYSCTRL_01

Resets Occurring in a Specific 2MHz Period During Initial Power Up are Incorrectly Reported

Revisions Affected:

Revision C

Details:

If a reset occurs in a specific 2MHz period during the initial power-up (boot), the reset source in AON_PMCTL.RESETCTL.RESET_SRC is reported as PWR_ON regardless of the reset source. This means there is a window of 0.5μs during boot where a reset can be incorrectly reported.

Workaround:

None