SWRZ138A July 2023 – August 2024 AWRL1432
Shared RAM clock gating default values
AWRL1432 ES1.1, ES2.0
Possibility of Shared RAM data corruption while exiting from deep sleep mode when clock gating registers are not reprogrammed.
The reset value for Front End Controller Sub System (FECSS), Application Sub System (APPSS) and Hardware Accelerator Sub System (HWASS) shared memory clock gate control is 1 . The clock ICG controls are coming from the following registers.
| Bits | Name |
Address |
|---|---|---|
| 0 | LPRADAR:FEC_CTRL:FECSS_SHARED_MEM_CLK_GATE : FECSS_SHARED_MEM_CLK_GATE_HWA_ENABLE |
0x5200002C |
| 0 | LPRADAR:APP_CTRL:APPSS_SHARED_MEM_CLK_GATE:APPSS_SHARED_MEM_CLK_GATE_MEM0_HWA_ENABLE |
0x56060398 |
| 2 | LPRADAR:APP_CTRL:APPSS_SHARED_MEM_CLK_GATE:APPSS_SHARED_MEM_CLK_GATE_MEM1_HWA_ENABLE | 0x56060398 |
When APPSS tries to access shared memory bank 0 via VBUSM SCR while FECSS is accessing shared memory via AHB, wrong read values of zero from the shared RAM on the APPSS is observed .
If only one of the clock gates (either HWA or FEC/APP) is enabled based on the allocation, the data is read correctly. Since the clock gating controls are coming from control registers space, these values get reset again and hence needs to be re-programmed after every deep sleep exit.
Program ICG controls of clock reaching to shared memory based on different shared memory configuration. The ICG control needs to be re-programmed after every deep sleep exit too.
| Configuration | Software care-about |
|---|---|
| Memory is shared with M3 | Disable the following ICG control :-LPRADAR:FEC_CTRL:FECSS_SHARED_MEM_CLK_GATE : FECSS_SHARED_MEM_CLK_GATE_HWA_ENABLE |
| First 128kb is shared with M4 | Disable the following ICG control :- LPRADAR:APP_CTRL:APPSS_SHARED_MEM_CLK_GATE:APPSS_SHARED_MEM_CLK_GATE_MEM0_HWA_ENABLE |
| 256kb is shared with M4 | Disable the following ICG controls:
|