SWRZ138A July   2023  – August 2024 AWRL1432

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1. 5.1  ANA #51
    2. 5.2  ANA #52
    3. 5.3  DIG #1
    4. 5.4  DIG #2
    5. 5.5  DIG #3
    6. 5.6  DIG #4
    7. 5.7  DIG #5
    8. 5.8  DIG #6
    9. 5.9  DIG #7
    10. 5.10 DIG #8
    11. 5.11 DIG #9
    12. 5.12 DIG #10
    13. 5.13 DIG #14
    14. 5.14 DIG #15
    15. 5.15 DIG #16
  7. 6Trademarks
  8.   Revision History

5.13 DIG #14

Corrupted Data Store for Partial Write in Shared Memory

Revision(s) Affected

AWRL1432 ES1.1, ES2.0

Details

Internal shared memory has ODD and EVEN banking structure. For a particular address range, partial write (less than 32 bit) to EVEN bank corrupts same address of ODD bank with next data on the bus. When shared memory is allocated to M4/M3, back to back full word write access to location A followed by sub-word write access to location B corrupts data in location A.

When memory is shared with M4/M3, issue is seen in the following address range:

Memory Address Range
APP_CPU_SHARED_RAM 0x0048 0000 - 0x004B FFFC
FEC_CPU_SHARED_RAM 0x2120 8000 - 0x2121 FFFC
AWRL1432 Shared Memory Logic Diagram When Shared with M4/M3 Figure 5-1 Shared Memory Logic Diagram When Shared with M4/M3

When shared with M3/M4, the incoming data bit width is 32 bit as shown in the diagram. So, depending on LSB of address, signals are sent to either left or right ECC wrapper.

Workaround

  1. Use shared memories as code memory when shared with processor.
  2. Disable ECC for non functional safety devices – ECC is disabled for shared memories in RBL for non functional safety devices.