SWRZ155 December   2024 AWRL6844

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1. 5.1 ANA #51
    2. 5.2 DIG #17
  7. 6Trademarks
  8.   Revision History

5.2 DIG #17

HWA CFAR CA engine is not working if dynamic clock gating is enabled

Revision(s) Affected

AWRL684x ES1.0

Details

Dynamic clock gating feature is added in IP for power savings. Idea is to enable clock to the FFT/CFAR-CA/CFAR-OS engine only when the respective engine is needed to be active based on the mode of operation. However, when CFAR CA engine is enabled and dynamic clock gating is set, the clock to one of the logic in the engine gets gated. Due to this, the data transfer to the logic internal to the CFAR-CA engine gets hampered. Hence, we do not get any valid data in the output of the CFAR CA engine.

Workaround

Disable the dynamic clock gating feature when CFAR CA mode of operation is enabled.