SWRZ162 May   2024 IWR2944

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#27
    3.     MSS#28
    4.     MSS#29
    5.     MSS#30
    6.     MSS#33
    7.     MSS#40
    8. 5.1  MSS#46
    9. 5.2  MSS#48
    10. 5.3  MSS#49
    11. 5.4  MSS#52
    12. 5.5  MSS#53
    13. 5.6  MSS#54
    14. 5.7  MSS#55
    15. 5.8  MSS#56
    16. 5.9  MSS#57
    17. 5.10 MSS#58
    18. 5.11 MSS#59
    19. 5.12 MSS#60
    20. 5.13 MSS#61
    21. 5.14 MSS#62
    22. 5.15 ANA#12A
    23.     ANA#32A
    24.     ANA#33A
    25.     ANA#34A
    26.     ANA#35A
    27.     ANA#36
    28.     ANA#37A
    29.     ANA#38A
    30.     ANA#39
    31.     ANA#43
    32.     ANA#44
    33.     ANA#45
    34.     ANA#46
    35.     ANA#47
  7.   Trademarks
  8. 6Revision History

MSS#61

Data aborts seen while access made to last 24 bytes of the configured MPU region and cache is enabled.

Revision(s) Affected

IWR2944 ES1.0, ES2.0

Details

When R5F performs access to a byte or word in the cacheable region, the access from cache is 32bytes long (One cache line size) with the starting address being the critical word being fetched.

The MPU assumes (Incorrectly) that the end address of the ongoing transaction to be Critical word + 32Bytes and compares this with the end address programmed in the MPU. MPU treats this as access violation and faults the transaction (Ex : 0x701FFFF8 + 32 byte = 0x7020 0018 > 0x70FF FFFF).

This issue is not applicable if MPU regions are marked as non-cacheable.

Workaround

If Cache is enabled, do not have any data in the last 32Bytes of the MPU region.