Revision(s) Affected

AWR2944P, AWR2E44P

Details

When R5F performs access to a byte or word in the cacheable region, the access from cache is 32bytes long (One cache line size) with the starting address being the critical word being fetched.

The MPU assumes (Incorrectly) that the end address of the ongoing transaction to be Critical word + 32Bytes and compares this with the end address programmed in the MPU. MPU treats this as access violation and faults the transaction (Ex : 0x701FFFF8 + 32 byte = 0x7020 0018 > 0x70FF FFFF).

This issue is not applicable if MPU regions are marked as non-cacheable.

Workaround

If Cache is enabled, do not have any data in the last 32Bytes of the MPU region.