SWRZ166 November   2024 AWR2944P

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#27
    3.     MSS#28
    4.     MSS#29
    5.     MSS#30
    6.     MSS#33
    7.     MSS#40
    8. 5.1  MSS#49
    9. 5.2  MSS#52
    10. 5.3  MSS#53
    11. 5.4  MSS#54
    12. 5.5  MSS#55
    13. 5.6  MSS#56
    14. 5.7  MSS#57
    15. 5.8  MSS#61
    16. 5.9  MSS#62
    17.     MSS#66
    18. 5.10 MSS#67
    19. 5.11 ANA#12A
    20.     ANA#37A
    21.     ANA#39
    22.     ANA#43
    23.     ANA#44
    24.     ANA#45
    25.     ANA#46
    26.     ANA#47
  7.   Trademarks
  8.   Revision History

MSS#27

MibSPI in Peripheral Mode in 3- or 4-Pin Communication Transmits Data Incorrectly for Slow SPICLK Frequencies and for Clock Phase = 1

Revision(s) Affected:

AWR2944P, AWR2E44P

Description:

The MibSPI module, when configured in multibuffered peripheral mode with 3-functional pins (CLK, SIMO, SOMI) or 4-functional pins (CLK, SIMO, SOMI, nENA), could transmit incorrect data when all the following conditions are met:

  • MibSPI module is configured in multibuffered mode,
  • Module is configured to be a peripheral in the SPI communication,
  • SPI communication is configured to be in 3-pin mode or 4-pin mode with nENA,
  • Clock phase for SPICLK is 1, and
  • SPICLK frequency is MSS_VCLK frequency / 12 or slower

Workaround(s):

The issue can be avoided by setting the CSHOLD bit in the control field of the TX RAM (Multi-Buffer RAM Transmit Data Register). The nCS is not used as a functional signal in this communication; hence, setting the CSHOLD bit does not cause any other effect on the SPI communication.