TIDT239A April   2021  – July 2021

 

  1. 1Description
  2. 2Test Prerequisites
    1. 2.1 Voltage and Current Requirements
    2. 2.2 Dimensions
  3. 3Testing and Results
    1. 3.1 Switching Frequency
    2. 3.2 Standby Power Consumption
    3. 3.3 Tiny Load Power Consumption
    4. 3.4 Average and 10% Load Efficiency
    5. 3.5 Efficiency Graphs
    6. 3.6 Thermal Images
    7. 3.7 Bode Plots
    8. 3.8 EMI
  4. 4Waveforms
    1. 4.1 Switching
    2. 4.2 Output Voltage Ripple
    3. 4.3 Load Transients
    4. 4.4 Voltage Transitions
      1.      Trademarks
  5. 5Revision History

Switching

Switching behavior at 265 VAC, 50-Hz input is shown in the following figures. The highest voltage stress on both primary and secondary FETs occurs at highest input voltage and highest output voltage conditions. The voltage stress is highest on the synchronous rectifier (SR) FET during light loads when the UCC28782 disables ZVS operation to improve light load efficiency. At this condition, the non-ZVS results in a low-energy, high frequency spike on the drain of the SR FET.

GUID-20210404-CA0I-LB2F-JBQX-SZ6RLXH8PRLP-low.jpgFigure 4-1 Primary FET (Q2) Drain-Source Voltage at 20 V, 3.25-A Output
GUID-20210404-CA0I-QFDP-0NKV-33H0F4NFKGZJ-low.jpgFigure 4-3 SR FET (Q5) Drain-Source Voltage at 20 V, 0-A Output
GUID-20210404-CA0I-MSMM-ZXZD-3V4WZPFZMJNG-low.jpgFigure 4-2 SR FET (Q5) Drain-Source Voltage at 20 V, 3.25-A Output