TIDT262 April   2022

 

  1.   Description
  2.   Features
  3.   Applications
  4. 1Test Prerequisites
    1. 1.1 Voltage and Current Requirements
    2. 1.2 Considerations
    3. 1.3 Dimensions
  5. 2Testing and Results
    1. 2.1 Efficiency Graphs
    2. 2.2 Load Regulation
    3. 2.3 Line Regulation
    4. 2.4 Thermal Images
      1. 2.4.1 Further Extensive Thermal Measurements
        1. 2.4.1.1 No Forced Cooling
          1. 2.4.1.1.1 Thermal Images 4.5 VIN and 20 AOUT
            1. 2.4.1.1.1.1 After 1 Minute of Operation
            2. 2.4.1.1.1.2 After 2 Minutes of Operation
          2. 2.4.1.1.2 Thermal Image 5.5 VIN and 20 AOUT
          3. 2.4.1.1.3 Thermal Image 7 VIN and 25 AOUT
          4. 2.4.1.1.4 Thermal Image 9 VIN and 30 AOUT
          5. 2.4.1.1.5 Thermal Image 12 VIN and 30 AOUT
          6. 2.4.1.1.6 Thermal Image 15 VIN and 30 AOUT
          7. 2.4.1.1.7 Thermal Image 13.8 VIN and 30 AOUT
        2. 2.4.1.2 Forced Cooling
          1. 2.4.1.2.1 Thermal Image 4.5 VIN and 20 AOUT
          2. 2.4.1.2.2 Thermal Image 5.5 VIN and 20 AOUT
          3. 2.4.1.2.3 Thermal Image 7 VIN and 25 AOUT
          4. 2.4.1.2.4 Thermal Image 9 VIN and 30 AOUT
          5. 2.4.1.2.5 Thermal Image 12 VIN and 30 AOUT
          6. 2.4.1.2.6 Thermal Image 15 VIN and 30 AOUT
    5. 2.5 Bode Plots
  6. 3Waveforms
    1. 3.1 Switching
      1. 3.1.1 9-V Input Voltage (Boost Mode)
        1. 3.1.1.1 Boost High Side FETs (Q5, Q6)
          1. 3.1.1.1.1 Source-Drain (Referenced to VOUT')
          2. 3.1.1.1.2 Gate-Source
        2. 3.1.1.2 Boost Low Side (Q7, Q8)
          1. 3.1.1.2.1 Drain-GND
          2. 3.1.1.2.2 Gate-GND
      2. 3.1.2 12-V Input Voltage, Transition Mode, Both Legs Switching at ½ FSW
        1. 3.1.2.1 Boost High Side FETs (Q5, Q6)
          1. 3.1.2.1.1 Source-Drain (Referenced to VOUT')
          2. 3.1.2.1.2 Gate-Source
        2. 3.1.2.2 Boost Low Side (Q7, Q8)
          1. 3.1.2.2.1 Drain-GND
          2. 3.1.2.2.2 Gate-GND
      3. 3.1.3 16-V Input Voltage, Buck Mode
        1. 3.1.3.1 Buck High Side FETs (Q1, Q2)
          1. 3.1.3.1.1 Source-Drain (Referenced to VIN')
          2. 3.1.3.1.2 Gate-Source
        2. 3.1.3.2 Buck Low Side (Q3, Q4)
          1. 3.1.3.2.1 Drain-GND
          2. 3.1.3.2.2 Gate-GND
    2. 3.2 Output Voltage Ripple
    3. 3.3 Input Voltage Ripple
      1. 3.3.1 Power Stage
      2. 3.3.2 Input Terminal, Differential Input Filter Acting
    4. 3.4 Load Transients
      1. 3.4.1 9-V Input Voltage
      2. 3.4.2 12-V Input Voltage
      3. 3.4.3 16-V Input Voltage
    5. 3.5 Start-Up Sequence
      1. 3.5.1 9-V Input Voltage
      2. 3.5.2 12-V Input Voltage
      3. 3.5.3 16-V Input Voltage
    6. 3.6 Shutdown Sequence
      1. 3.6.1 9-V Input Voltage
      2. 3.6.2 12-V Input Voltage
      3. 3.6.3 16-V Input Voltage

2.3 Line Regulation

Figure 2-4 shows the line regulation graph for output voltage versus input voltage.

GUID-20220303-SS0I-TFMV-6CMG-Q2MZNXTT5Q8F-low.jpg Figure 2-4 Output Voltage vs Input Voltage

At 5-V input voltage the output voltage was down regulated to 10.1 V due to current limit.

Figure 2-5 shows the efficiency and loss versus input voltage graph.

GUID-20220303-SS0I-BFWH-MLJK-ZGQC3GS2RTTP-low.jpg Figure 2-5 Efficiency and Loss vs Input Voltage