TIDT293 October 2022
This section describes the functional blocks in Figure 2-2 through Figure 2-5.
Either a standard 9-V battery or a bench supply of 6 V to 12 V powers the board through switch S1. There is a reverse current and voltage clamping diode to protect the source. The input power feeds into a 5-V linear regulator for the pulse timing and protection features. There is also a switching regulator controlling SEPIC and Ćuk converters that share a coupled 1:1 inductor. This produces a dual output of +12 V and –12 V for pulse shaping and driving circuitry.
A factory preset temperature sensor with integrated comparator is used to deliver a shutdown signal to the load switch driver during an overtemperature event. There are test points for monitoring the thermistor voltage (TP4) and to simulate a fault (TP5). When the output is pulled high, the load switch driver is shut down.
When the board is powered, an LED turns on to indicate battery voltage. Pgood (D7) is a green LED that indicates a good input supply. When Vbatt/Vin falls to 6 V, the Pgood LED turns off and the red LED, Low Battery (D8), turns on. When Vbatt/Vin rises to 7 V, the Low Battery LED turns off and the Pgood LED turns on.
This functions the same as pressing S2 every second to trigger the rest of the timing circuits. When J6 is connected, the output of U8 can now be pulled high or low depending on the voltage across capacitor C32. R35, R40, and C32 were chosen for short 1-Hz pulses pulled low to trigger the delay and period timers.
This block enables or disables the driver to set the amount of time the load step current is non-zero for each 1-second interval. The free run or S2 pulse triggers the period 555 timer. When the period output is high, Q8 turns on and grounds the driver power-down signal which enables the driver to turn on. The amount of time the driver is enabled depends on the period RC time constant set by potentiometer R36 and caps C33–C35 (modified by jumpers J8, J9). When Disable Zero J7 is installed, the driver power down signal is always grounded and the driver is always enabled.
Delay is important to allow time for the low-level period to be set before the high-level pulse to correctly shape the load step reference. The free run or S2 pulse triggers the delay 555 timer to pull the delay output high. The amount of time the delay output is high depends on the delay RC time constant set by potentiometer R46 and caps C43–C45 (modified by jumpers J10, J11).
This block determines the amount of time the load step board draws the high-level current. After the delay output falls low, the pulse width output gets pulled high. The amount of time the pulse output is high depends on the pulse width RC time constant set by potentiometer R47 and capacitors C46–C48 (modified by jumpers J12, J13). The Pulse (TP10) signal is then fed into the shaping portion of the board.
A reference voltage U5 is connected between ground by two potentiometers where the center tap of each sets a voltage at the inputs of a dual op amp. The way the potentiometers are connected makes it such that the high-level minimum voltage is the same as the set low-level voltage, which ranges between 0 and Vref. The op-amp outputs are tied to complimentary NFET and PFET switches driven by an amplified and level-shifted version of the Pulse signal (TP10) called DRV. The end result is a scaled version of Pulse (TP10) ranging from the low-level to high-level voltages.
To avoid overshoot and high-frequency ringing in the load step, this function slows down the slew rate of the reference voltage pulse and passes the pulse through a low-pass filter to get our INP reference for the driver (TP7). The settling time is controlled by modifying the RC time constant of the low-pass filter consisting of potentiometer R43 and capacitors C18–C20 (modified by jumpers J4, J5).
To slow the slew rate, the available charging and discharging current of C18–C20 is decreased by using 2 independent current mirrors to control positive and negative slew rates separately.
Q5 and Q6 form the positive slew control current mirror while Q3 and Q4 control the negative slew control current mirror. Increasing potentiometer R12 decreases the constant current source to charge C18–C20 on the rising edge of the pulse. Likewise, increasing potentiometer R58 decreases the constant current sink to discharge C18–C20 on the falling edge of the pulse.
Finally, the high bandwidth and low-noise load switch amplifier drives the gate of the load switch based on the INP (TP7) reference pulse. A current sense resistor R21 in the negative feedback trace scales the high- and low-level voltages of INP to high- and low-level currents for the load step. Additional filtering on the output of the amplifier determines the bandwidth limitation and R13 sets the amplifier gain for the gate drive. If the overtemperature or low-level period power down signals are pulled high, the driver shuts off the load switch and zero current is drawn.