TIDUBE5A January 2022 – October 2022
Table 3-7 shows the CPU cycles used, the CPU loading and available MIPs when a full implementation of InstaSPIN-FOC is used for dual motor control with PFC on F280025C with 100 MHz CPU, as well as users' code is loaded to FLASH, and the ISR code is copied to RAM for execution.
CPU=100MHz | Maximum CPU Cycles For ISR | Maximum CPU Utilization [%] | Maximum MIPS Used [MIPS] |
---|---|---|---|
PFC at PWM=72kHz, ISR= 36kHz | 465 | 16.74 | 16.74 |
Motor 1 at PWM=6kHz, ISR=6kHz | 2372 | 14.23 | 14.23 |
Motor 2 at PWM=18kHz, ISR=6kHz | 2226 | 13.36 | 13.36 |
Total Used CPU Utilization | 44.33 | 44.33 | |
Available CPU MIPS | 55.67 |
Table 3-8 shows the CPU cycles used, the CPU loading and available MIPs when a full implementation of eSMO is used for dual motor control with PFC on F280025C with 100 MHz CPU, as well as users' code is loaded to FLASH, and the ISR code is copied to RAM for execution.
F280025C CPU = 100 MHz Available MIPS = 100 MIPS | Maximum CPU Cycles For ISR | Maximum CPU Utilization [%] | Maximum MIPS Used [MIPS] |
---|---|---|---|
PFC at PWM = 72 kHz, ISR = 36 kHz | 465 | 16.74 | 16.74 |
Motor 1 at PWM = 6 kHz, ISR = 6 kHz | 1745 | 10.47 | 10.47 |
Motor 2 at PWM = 18 kHz, ISR = 6 kHz | 1568 | 9.41 | 9.41 |
Total Used CPU Utilization [%] | 36.62 | ||
Available CPU MIPS [MIPS] | 63.38 |
Table 3-9 shows the CPU cycles used, the CPU loading and available MIPs when a full implementation of InstaSPIN-FOC is used for dual motor control with PFC on F280039C/F2800137 with 120 MHz CPU, as well as users' code is loaded to FLASH, and the ISR code is copied to RAM for execution.
CPU=120MHz | Maximum CPU Cycles For ISR | Maximum CPU Utilization [%] | Maximum MIPS Used [MIPS] |
---|---|---|---|
PFC at PWM=72kHz, ISR= | 465 | 13.95 | 16.74 |
Motor 1 at PWM=6kHz, ISR=6kHz | 2372 | 11.86 | 14.23 |
Motor 2 at PWM=18kHz, ISR=6kHz | 2226 | 11.13 | 13.36 |
Total Used CPU Utilization [%] | 36.94 | ||
Available CPU MIPS [MIPS] | 75.67 |
Table 3-10 shows the CPU cycles used, the CPU loading and available MIPs when a full implementation of eSMO is used for dual motor control with PFC on F280039C/F2800137 with 120MHz CPU, as well as users' code is loaded to FLASH, and the ISR code is copied to RAM for execution.
F280039C CPU = 120 MHz Available MIPS = 120 MIPS | Maximum CPU Cycles For ISR | Maximum CPU Utilization [%] | Maximum MIPS Used [MIPS] |
---|---|---|---|
PFC at PWM = 72 kHz, ISR = 32 kHz | 465 | 13.95 | 16.74 |
Motor 1 at PWM = 6kHz, ISR = 6kHz | 1745 | 8.72 | 10.47 |
Motor 2 at PWM = 18kHz, ISR = 6kHz | 1568 | 7.84 | 9,41 |
Total Used CPU Utilization [%] | 30.52 | ||
Available CPU MIPS [MIPS] | 83.38 |