This camera module reference design addresses the need for small low-cost cameras in automotive driver assistance systems (ADAS) by combining a 1.3-megapixel imager with integrated image signal processor (ISP) with a 12-bit, 100-MHz TI FPD-Link III serializer. Additionally, it provides a power-management integrated circuit (PMIC) power supply for both devices in an ultra-small form factor. This design includes a high-speed serial interface to connect a remote automotive camera module to a display or machine vision processing system with a coaxial cable transmitting both data and power. The FPD-Link III SerDes technology used in this reference design enables the transmission of raw or processed video data, bidirectional control signals, and power over coax (POC) using a single cable.
TIDA-050050 | Design Folder |
TPS650330-Q1 | Product Folder |
DS90UB933-Q1 | Product Folder |
Many automotive applications require small form factors with reduced circuit area that enable compact and modular systems. As a result, most cameras along with electronic components must meet this minimal area constraint when designing ADAS camera applications. This reference design addresses these needs by including a 1-megapixel imager, 1.9 Gbps serializer, and a single Power Management IC, and all components contained within an area of an 18-mm × 18-mm circuit board. The only connection required by the system is a single 50-Ω coaxial cable.
A combined signal containing the DC power, the FPD-Link front and back channels enter the board through the FAKRA coax connector. The filter in Figure 1-1 blocks all of the high-speed content of the signal (without significant attenuation) while allowing the DC (power) portion of the signal to pass through inductor L5.
The DC portion is connected to the buck 1 input of the TPS650320-Q1 Power Management IC. This voltage powers buck 2 and buck 3 of the device, which are responsible for creating the supply rails to the imager and serializer. The LDO input pin is supplied 3.8 V, which is responsible for providing a low-noise, 3.3-V analog supply to the imager. Buck 3 outputs the imager-dedicated 1.1-V and buck 2 generates a universal 1.8-V digital supply that is shared by both the imager and serializer. The high-frequency portion of the signal is connected directly to the serializer. This is the path that the video data and the control back channel takes between the serializer and deserializer.
The output of the imager is connected through a parallel digital video port (DVP) interface to the serializer. The serializer transmits this video data over a single LVDS pair to the deserializer located on the other end of the coax cable.
Additionally, on the same coax cable, there is a separate low-latency, bidirectional control channel that provides the additional function of transmitting control information from an I2C port. This control channel is independent of the video blanking period. It is used by the system microprocessor to configure and control the imager.
PARAMETER | COMMENTS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIN | Supply voltage | Power over coax (POC) | 4.5 | 9 | 18.3 | V |
PTOTAL | Total power consumption | VPOC = 12 V | — | 0.6 | 1 | W |
APCB | PCB Area | — | — | 18 x 18 | mm2 |
The following subsections discuss the considerations behind the design of each subsection of the system.
This reference design is not intended to fit any particular form factor; however, the goal of the design is to showcase a solution with minimal PCB area and compact design. The area of the board roughly equates to a dimension of 18 mm × 18 mm. The area near the board edge in Figure 2-2 is reserved for attaching the optics housing that holds the lens.
One of the most critical portions of a design that uses POC is the filter circuitry. The goal is twofold:
The DS90UB933-Q1 and DS90UB954-Q1 SerDes devices used in this system communicate over two carrier frequencies, 1 GHz at full speed ("forward channel") and a lower frequency of 2.5 MHz ("back channel") determined by the deserializer device. The filter must attenuate this rather large band spanning both carriers, hoping to pass only DC.
For the POC design, to enable the forward channel and back channel to pass uninterrupted over the coax, an impedance of 1 kΩ across the 1-MHz to 1-GHz bandwidth is required. Use two inductors: a 4.7-µH inductor for high-frequency forward channel filtering, and a 100-µH inductor for low-frequency back-channel filtering. For more details, see the Sending Power Over Coax in DS90UB913A Designs application report. In addition, a 1-kΩ resistor is placed in parallel with both of these inductors. A 1-kΩ ferrite bead is also placed in series for extra filtering at the forward channel data rate.
Lastly, in regards to filtering, ensuring that the FPD-Link signal is uninterrupted is just as important as providing a clean, noise-free DC supply to the system. To achieve this, AC coupling capacitors shown by the 0.1 µF and 0.047 µF are chosen to ensure the high-speed AC data signals are passed through but that the DC is blocked from getting on the data lines.
Because this reference design is targeted at automotive applications, there are several considerations that limit design choices. Additionally, the following list of system-level specifications helped shape the final overall design:
Before parts are chosen, the input voltage range, required voltage rails, and required current per rail must be known. In this case, the input voltage is a pre-regulated 9-V supply coming in over the coaxial cable. This system has only two main devices, the imager and serializer, which are responsible for power consumption during operation. Table 2-1 shows the requirements of the supplies:
PARAMETER | VOLTAGE (V) | CURRENT (mA) | POWER (mW) |
---|---|---|---|
DS90UB933 | |||
VDD | 1.8 | 98 | 176 |
OX01F10 | |||
VDD-D | 1.1 | 170 | 187 |
VDD-IO | 1.8 | 21 | 38 |
VDD-A | 3.3 | 33 | 109 |
Oscillator | |||
VDD | 1.8 | 3 | 5 |
Total | |||
VDD-D | 1.1 | 170 | 187 |
VDD-IO | 1.8 | 122 | 220 |
VDD-A | 3.3 | 33 | 109 |
The9-V supply over the coaxial cable is first stepped down to 3.8 V, which then supplies the rest of the system on the camera module. In this design, the 1.8-V rail supplies both the DS90UB933 supply, and the interface supply of the OX01F10 imager. The OX01F10 3.3-V analog rail requires 33 mA, the DS90UB933 serializer 1.8-V rail requires 98 mA, and the OX01F10 digital 1.1-V rail requires 170 mA.
Assuming 85% efficiency to simplify calculations with the previous values, it is calculated that the 3.8-V supply will require 160 mA to successfully power the 1.1-V, 1.8-V, and 3.3-V rails. Because the input and output voltages, output current requirements, and total wattage consumption are known, calculate the input current using Equation 5:
This information provides a strong foundation in the selection of power topologies and inductive passives that are explained in later sections.
Due to the requirement of Q100, it is mandatory that the switching frequency is rated outside of the AM band and must satisfy the voltage and current requirements derived previously. As the input voltage is a regulated voltage that will always be greater than any of the power rails produced, the power topologies selected should either be step-down converters (bucks) or LDOs. Bucks are generally included in supplies where switching noise is not a significant concern, and power savings is the largest care about. Conversely, LDOs can be incorporated in establishing low-noise analog supplies that reduce inherent noise and are more robust against EMI interactions; however, this is at the expense of larger current consumption.
In this design, a single Power Management IC is responsible for powering the supply rails. This device, the TPS650320-Q1, was chosen as it incorporates three step-down converters (BUCKS) and an LDO in a single 4.0-mm x 4.0-mm VQFN package. The current requirements of the design also played an important role in the selection of the device, as the secondary BUCKS are capable of providing 600 mA, while the LDO is capable of supplying a maximum current output of 300 mA. BUCK1 steps down the 9-V POC input to 3.8 V. The 3.8-V rail then supplies power to BUCK2, BUCK3, and the LDO input. BUCK 2 provides the interface and digital supply for both the OX01F10 imager and DS90UB933 serializer, while the LDO output creates a clean, low-noise supply for the 3.3-V analog supply for the OX01F10.
For simplicity, the efficiency of the buck regulators is assumed to be 85% for these operating conditions, and the efficiency of the LDO is given by Equation 5.
Table 2-2 shows the load capability of each regulator compared to the requirements of the camera module. The TPS650320-Q1 device is capable of supplying the system power with plenty of margin to account for variations between typical and maximum current variation.
REGULATOR | OUTPUT VOLTAGE (V) | MAX CURRENT (mA) | REQUIRED CURRENT (mA) |
---|---|---|---|
Buck 1 | 3.8 | 800 | 160 |
Buck 2 | 1.8 | 600 | 122 |
Buck 3 | 1.1 | 600 | 170 |
LDO | 3.3 | 300 | 33 |
After determining that the TPS650320-Q1 device is suitable based on the power requirements, the external components can be chosen quickly based on the data sheet recommendations, simplifying the design process. These recommendations are shown in Figure 2-5 and Equation 5.
COMPONENT | DESCRIPTION | VALUE | UNIT |
---|---|---|---|
CVSYS,VSYS_S | VSYS and VSYS_S decoupling | 10 | µF |
CPVIN_B1 | Buck 1 input capacitor | 10 | µF |
LSW_B1 | Buck 1 inductor | 2.2 | µH |
COUT_B1 | Buck 1 output capacitor | 10 | µF |
CPVIN_B2 | Buck 2 input capacitor | 10 | µF |
LSW_B2 | Buck 2 inductor | 1.0 | µH |
COUT_B2 | Buck 2 output capacitor | 10 | µF |
CPVIN_B3 | Buck 3 input capacitor | 10 | µF |
LSW_B3 | Buck 3 inductor | 1.0 | µH |
COUT_B3 | Buck 3 output capacitor | 10 | µF |
CPVIN_LDO | LDO input capacitor | 1.0 | µF |
COUT_LDO | LDO output capacitor | 2.2 | µF |
The high, fixed PWM 2.3-MHz switching frequency enables the use of small inductors with a fast transient response. A value of 2.2 µH is typically recommended for the BUCK1 channel output. This value helps to minimize the inductor ripple current.
With the inductance value chosen, the design now needs an inductor with a proper saturation current. This is the combination of the steady-state supply current as well as the inductor ripple current. The current rating needs to be sufficiently high but minimized as much as possible to reduce the physical size of the inductor. Calculate inductor ripple with Equation 3:
where:
The parameters for this reference design using the TPS650330-Q1 are:
These parameters yield an inductor current of ∆IL = 535 mA. The maximum current draw of the system through this regulator is 327 mA. The minimum saturation current is calculated as:
The TPS650330-Q1 device on this design uses a Murata® LQM2MPN2R2NG0, which has a rated current of 1.2 A and a DC resistance maximum of 138 mΩ. Additionally, this device has an operating temperature from –55°C to 125°C and comes in a very small 2-mm × 1.6-mm package.