TIDUC65 April   2022 TPSI3050 , TPSI3050-Q1 , TPSI3052 , TPSI3052-Q1

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
    3. 2.3 Design Considerations
      1. 2.3.1 Overcurrent Protection (OCP)
        1. 2.3.1.1 Immediate Overcurrent Protection
        2. 2.3.1.2 Adjustable Delay Overcurrent Protection
      2. 2.3.2 Overtemperature Protection (OTP)
        1. 2.3.2.1 TMP392
        2. 2.3.2.2 ISO7310
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Altium Project
      4. 4.1.4 Assembly Drawings
      5. 4.1.5 Gerber Files
    2. 4.2 Documentation Support
    3. 4.3 Support Resources
    4. 4.4 Trademarks
  10. 5About the Author

2.3.2.2 ISO7310

ISO7310 transfers signal to low voltage side as the input to the AND gate. The ISO7310-Q1 device provides galvanic isolation up to 3000 VRMS for 1 minute per UL 1577 and 4242 VPK per VDE V 0884-10. These devices have one isolated channel comprised of a logic input and output buffer separated by a silicon dioxide (SiO2 ) insulation barrier. Used in conjunction with isolated power supplies, the ISO7310-Q1 device prevents noise currents on a data bus or other circuit from entering the local ground and interfering with or damaging sensitive circuitry. The device has integrated noise filters for harsh industrial environment where short noise pulses might be present at the device input pins.

The ISO7310-Q1 device has TTL input thresholds and operates from 3 V to 5.5 V supply levels. Through innovative chip design and layout techniques, electromagnetic compatibility of the ISO7310-Q1 device has been significantly enhanced to enable system-level ESD, EFT, Surge and Emissions compliance.

The digital isolator is used to transfer the signal to the low voltage side as the input to SN74HCS09 AND gate to assert EN high when the user provides a high signal for EN.