TIDUCL0 January   2017

 

  1. 1 Description
  2. 2 Resources
  3. 3 Features
  4. 4 Applications
  5. 5 Design Images
  6. 6 System Overview
    1. 6.1 System Description
    2. 6.2 Key System Specifications
    3. 6.3 Block Diagram
    4. 6.4 Highlighted Products
      1. 6.4.1 CSD88584Q5DC
      2. 6.4.2 DRV8323
      3. 6.4.3 MSP430F5132
      4. 6.4.4 TPS54061
      5. 6.4.5 LMT87
  7. 7 System Design Theory
    1. 7.1 Power Stage Design—Battery Power Input to the Board
    2. 7.2 Power Stage Design—Three-Phase Inverter
      1. 7.2.1 Design Considerations in Paralleling MOSFETs
        1. 7.2.1.1 Conduction Phase
        2. 7.2.1.2 Switching Phase
      2. 7.2.2 Selecting the Sense Resistor
    3. 7.3 Power Stage Design—DRV8323 Gate Driver
      1. 7.3.1 Gate Drive Features of DRV8323
      2. 7.3.2 Current Shunt Amplifier in DRV8323
      3. 7.3.3 Protection Features in DRV8323
    4. 7.4 Power Stage Design—18-V to 3.3-V DC-DC Converter
    5. 7.5 Power Stage Design —Microcontroller MSP430
    6. 7.6 Power Stage Design—Hall Sensor Interface
    7. 7.7 Temperature Sensing
    8. 7.8 Power Stage Design—External Interface Options and Indications
      1. 7.8.1 Speed Control of Motor
      2. 7.8.2 Direction of Rotation—Digital Input
      3. 7.8.3 LED Indications
      4. 7.8.4 Signal Interface Connector for External Monitoring and Control
  8. 8 Getting Started Hardware and Software
    1. 8.1 Hardware
      1. 8.1.1 Connector Configuration of TIDA-00774
      2. 8.1.2 Programming of MSP430
      3. 8.1.3 Procedure for Board Bring-up and Testing
    2. 8.2 Software
      1. 8.2.1 System Features
      2. 8.2.2 Customizing the Reference Code
        1. 8.2.2.1 PWM_PERIOD
        2. 8.2.2.2 MAX_DUTYCYCLE
        3. 8.2.2.3 MIN_DUTYCYCLE
        4. 8.2.2.4 ACCEL_RATE
        5. 8.2.2.5 Block_Rotor_Duration
      3. 8.2.3 Configuring the DRV8323 Registers (drv8323.c)
      4. 8.2.4 Initializing SPI Communication Between DRV8323 and MSP430 (drv8323.h)
      5. 8.2.5 Running Project in Code Composer Studio (CCS)
  9. 9 Testing and Results
    1. 9.1 Test Setup
    2. 9.2 Test Data
      1. 9.2.1 Functional Tests
        1. 9.2.1.1 3.3-V Power Supply Generated by Step-Down Converter
        2. 9.2.1.2 Gate Drive Voltage Generated by Gate Driver
        3. 9.2.1.3 Dead Time From DRV8323
        4. 9.2.1.4 MOSFET Switching Waveforms
        5. 9.2.1.5 VGS Skew of Parallel FETs During Switching
      2. 9.2.2 Load Test
        1. 9.2.2.1 Load Test Without Heat Sink
        2. 9.2.2.2 Load Test With Heat Sink
        3. 9.2.2.3 Load Test With Heat Sink and Airflow
      3. 9.2.3 Inverter Efficiency Test
      4. 9.2.4 Thermal Rise at Different Power Levels
      5. 9.2.5 Inverter Current Sensing by VDS Monitoring
      6. 9.2.6 Overcurrent and Short-Circuit Protection Test
        1. 9.2.6.1 Cycle-by-Cycle Stall Current Protection by DRV8323 VDS Sensing
        2. 9.2.6.2 Stall Current Latch Protection by DRV8323 VDS Sensing
      7. 9.2.7 Testing for Peak Current Capability
  10. 10Design Files
    1. 10.1 Schematics
    2. 10.2 Bill of Materials
    3. 10.3 PCB Layout Recommendations
      1. 10.3.1 Layout Prints
    4. 10.4 Altium Project
    5. 10.5 Gerber Files
    6. 10.6 Assembly Drawings
  11. 11Software Files
  12. 12Related Documentation
    1. 12.1 Trademarks
  13. 13Terminology
  14. 14About the Author

7.2.1.2 Switching Phase

The current sharing during the switching phase of the FET is affected by asymmetries in the gate drive circuit, differences in the circuit parasitics, and variations in device parameters such as transconductance gFS, threshold voltage VTH, and the input capacitances CGD and CGS. The effects of each parameter on current sharing are as follows:

  • In order for all the FETs to be turned on at the same time, the gate drive circuit for each FET has to be very similar. The gate charge current for each parallel FET has to be equal. The gate voltage applied by the gate driver must be the same. Also there should be no skew in the gate-to-source voltages applied to the different FETs. If all these parameters are kept within a tight tolerance, the dynamic load current sharing of the paralleled FETs remains equal. One way to keep all these parameters in tight tolerance is to use a single gate driver IC to drive all the parallel FETs. This ensures minimal skew between the VGS of FETs and the VGS voltage remains the same. The gate current into each FET can be maintained close to each other by choosing gate resistor values that have a tight tolerance. The gate path impedance has to be kept same in routing and this is possible by use of the miniature power blocks.
  • Circuit parasitics like the source (LS) and drain (LD) inductances affect the turnon and turnoff times of the FET. If one FET has a higher LS compared to the others, a higher voltage is induced across LS when current flows through it. This reduces the effective VGS applied to the FET, which in turn slows down the turnon time of the FET effecting dynamic current sharing. One solution to this is by making the layout symmetric so that the LS and LD of each of the FETs are close to each other. Matching LS and LD also ensures that the rise and fall times of current in each FET is close.
  • The threshold voltage of FETs is another important parameter affecting current sharing. The FET having the lowest VTH turns on first and carries the highest current. Therefore, the FETs selected should have a tight tolerance in VTH. Usually the FETs from one production batch have VTH close enough that by the time the current through one FET rises significantly, the gate voltage of other FETs reach their VTH reasonably quick and start conducting. Also, it is important to have individual gate resistances for each of the FET. If individual gate resistances are absent and all the gates are shorted together, then the FET—which reaches its VTH first—goes into the Miller region faster and clamps the gate of the other FETs to its Miller voltage, which further slows down the gate voltages of the remaining FETs. This significantly effects the turn on behavior. VTH is also dependent on temperature. The higher the temperature, the lower the VTH; this ensures that the FET turns on even faster, which may lead to runaway conditions. Therefore, it is important to maintain all the FETs at equal temperature. Distributing the heat in the PCB by extending the copper planes helps here.
  • Transconductance gFS of the FET also affects the dynamic current sharing between the FETs. The FET with the highest gFS has a faster rate of change of drain current with change in the gate-to-source voltage. So, during turnon, the FET with the highest gFS conducts the most current, and during turnoff the FET with the lowest gFS conducts current for a longer time.
  • The input gate-to-source capacitance CGS and gate-to-drain capacitance CGD also affect dynamic current sharing. If the gate drive for all the FETs is symmetric (that is, drive voltages and currents are equal), then the FET with the lowest input capacitance CISS reaches its threshold voltage first and conducts the most current during turnon. During turnoff, the FET with the highest input capacitance reaches its threshold voltage last and conducts current for a longer time. To reduce the impact of the input capacitance on current sharing, it is important to use individual gate resistors with low values.

    • Using low values ensures that all the FETs with variations in CISS reach their threshold values fairly close to each other. Selecting gate resistors is a trade-off between suppressing circulating currents and suppressing the effect of variations in CISS and VTH.