TIDUD32A June   2017  – January 2023

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 TPS82130
    3. 2.3 Design Considerations
      1. 2.3.1 Inverting Buck-Boost Topology Concept
      2. 2.3.2 VIN and VOUT Range
      3. 2.3.3 Maximum Output Current
        1. 2.3.3.1 Thermal Limits
        2. 2.3.3.2 Stability Limits and Output Capacitor Selection
      4. 2.3.4 Design Precautions
      5. 2.3.5 Enable Pin Configuration
      6. 2.3.6 Power Good Pin Configuration
      7. 2.3.7 Discharging Output Voltage
      8. 2.3.8 Adjustable Soft-Start Time
      9. 2.3.9 Input Capacitor Selection
  8. 3Getting Started Hardware
  9. 4Testing and Results
  10. 5Design Files
    1. 5.1 Schematics
    2. 5.2 Bill of Materials
    3. 5.3 PCB Layout Recommendations
      1. 5.3.1 Layout Prints
    4. 5.4 Gerber Files
    5. 5.5 Assembly Drawings
  11. 6Related Documentation
  12. 7Trademarks
  13. 8Revision History

2.3.5 Enable Pin Configuration

The device is enabled when the voltage at the EN pin trips its threshold and the input voltage is above the undervoltage lockout (UVLO) threshold. The TPS82130 device stops operation when the voltage on the EN pin falls below its threshold or the input voltage falls below the UVLO threshold.

Because VOUT is the IC ground in this configuration, the EN pin must be referenced to VOUT instead of ground. In the buck configuration, 0.9 V is considered as high and less than 0.3 V is considered as low. In the inverting buck-boost configuration, however, the VOUT voltage is the reference; therefore, the high threshold is 0.9 V + VOUT and the low threshold is 0.3 V + VOUT. For example, if VOUT = –5 V, then VEN is considered at a high level for voltages above –4.1 V and a low level for voltages below –4.7 V.

This behavior can cause difficulties enabling or disabling the part because, in some applications, the IC providing the EN signal may not be able to produce negative voltages. The level-shifter circuit that Figure 2-7 shows removes any difficulties associated with the offset EN threshold voltages by eliminating the requirement for negative EN signals. If disabling the TPS82130 is not desired, the EN pin may be directly connected to VIN without this circuit.

GUID-0FC03CE7-73A5-4F71-B605-B11B385674DF-low.gif
VOUT is the negative output voltage of the inverting buck-boost converter
Figure 2-7 EN Pin Level Shifter

The positive signal that originally drove EN is instead tied to the gate of Q1 (SYS_EN). When Q1 is OFF (SYS_EN grounded), Q2 has 0 V across its VGS and also remains OFF. In this state, the EN pin is initially at the level of the output voltage (–5 V), which is below the low-level threshold, and disables the device.

When SYS_EN provides enough positive voltage to turn Q1 ON (VGS threshold as specified in the MOSFET data sheet), the gate of Q2 is at ground potential through Q1. This action drives the VGS of Q2 negative and turns Q2 ON. Then VIN ties to EN through Q2 and the pin is above the high-level threshold, which turns the device ON. Be careful to ensure that the VGD and VGS of Q2 remain within the MOSFET ratings during both the enabled and disabled states. Failing to adhere to this constraint can result in damaged MOSFETs.

Figure 4-17 and Figure 4-18 show the enable and disable sequence. The SYS_EN signal activates the enable circuit and the G/D node signal represents the shared node between Q1 and Q2. This circuit has been tested with a 5-V SYS_EN signal and dual N/PFET Si1029X. The EN signal is the output of the circuit and goes from VIN to VOUT to properly enable and disable the device. The PG pin is used as an output discharge to accelerate the return of VOUT to 0 V, when the IC is disabled.