TIDUD61E October   2020  – April 2021

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Input AC Voltage Sensing
      2. 2.2.2 Bus Voltage Sensing
      3. 2.2.3 AC Current Sensing
      4. 2.2.4 Sense Filter
      5. 2.2.5 Protection (CMPSS)
    3. 2.3 Highlighted Products
      1. 2.3.1 C2000™ MCU F28004x
      2. 2.3.2 LMG3410R070
      3. 2.3.3 UCC27714
    4. 2.4 System Design Theory
      1. 2.4.1 PWM
      2. 2.4.2 Current Loop Model (PFC and Inverter mode)
      3. 2.4.3 DC Bus Regulation Loop (for PFC mode only)
      4. 2.4.4 Soft Start Around Zero Crossing for Eliminate or Reduce Current Spike
      5. 2.4.5 AC Drop Test
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Base Board Settings
        2. 3.1.1.2 Control Card Settings
      2. 3.1.2 Software
        1. 3.1.2.1 Opening Project Inside CCS
        2. 3.1.2.2 Project Structure
        3. 3.1.2.3 Using CLA on C2000 MCU to Alleviate CPU Burden
        4. 3.1.2.4 CPU and CLA Utilization and Memory Allocation
        5. 3.1.2.5 Running the Project
          1. 3.1.2.5.1 Lab 1: Open Loop, DC (PFC Mode)
            1. 3.1.2.5.1.1 Setting Software Options for LAB 1
            2. 3.1.2.5.1.2 Building and Loading Project
            3. 3.1.2.5.1.3 Setup Debug Environment Windows
            4. 3.1.2.5.1.4 Using Real-Time Emulation
            5. 3.1.2.5.1.5 Running Code
          2. 3.1.2.5.2 Lab 2: Closed Current Loop DC (PFC)
            1. 3.1.2.5.2.1 Setting Software Options for Lab 2
            2. 3.1.2.5.2.2 Designing Current Loop Compensator
            3. 3.1.2.5.2.3 Building and Loading Project and Setting up Debug
            4. 3.1.2.5.2.4 Running Code
          3. 3.1.2.5.3 Lab 3: Closed Current Loop, AC (PFC)
            1. 3.1.2.5.3.1 Setting Software Options for Lab 3
            2. 3.1.2.5.3.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.3.3 Running Code
          4. 3.1.2.5.4 Lab 4: Closed Voltage and Current Loop (PFC)
            1. 3.1.2.5.4.1 Setting Software Options for Lab 4
            2. 3.1.2.5.4.2 Designing Voltage Loop Compensator
            3. 3.1.2.5.4.3 Building and Loading Project and Setting up Debug
            4. 3.1.2.5.4.4 Running Code
          5. 3.1.2.5.5 Lab 5: Open loop, DC (Inverter)
            1. 3.1.2.5.5.1 Setting Software Options for Lab 5
            2. 3.1.2.5.5.2 Building and Loading Project
            3. 3.1.2.5.5.3 Setup Debug Environment Windows
            4. 3.1.2.5.5.4 Running Code
          6. 3.1.2.5.6 Lab 6: Open loop, AC (Inverter)
            1. 3.1.2.5.6.1 Setting Software Options for Lab 6
            2. 3.1.2.5.6.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.6.3 Running Code
          7. 3.1.2.5.7 Lab 7: Closed Current Loop, DC (Inverter with resistive load)
            1. 3.1.2.5.7.1 Setting Software Options for Lab 7
            2. 3.1.2.5.7.2 Designing Current Loop Compensator
            3. 3.1.2.5.7.3 Building and Loading Project and Setting up Debug
            4. 3.1.2.5.7.4 Running Code
          8. 3.1.2.5.8 Lab 8: Closed Current Loop, AC (Inverter with resistive load)
            1. 3.1.2.5.8.1 Setting Software Options for Lab 8
            2. 3.1.2.5.8.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.8.3 Running Code
          9. 3.1.2.5.9 Lab 9: Closed Current Loop (Grid Connected Inverter)
            1. 3.1.2.5.9.1 Setting Software Options for Lab 9
            2. 3.1.2.5.9.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.9.3 Running Code: Emulated Grid-tied Condition (Verification purpose only)
            4. 3.1.2.5.9.4 Running Code: Grid-tied Condition
        6. 3.1.2.6 Running Code on CLA
        7. 3.1.2.7 Advanced Options
          1. 3.1.2.7.1 Input Cap Compensation for PF Improvement Under Light Load
          2. 3.1.2.7.2 83
          3. 3.1.2.7.3 Adaptive Dead Time for Efficiency Improvements
          4. 3.1.2.7.4 Phase Shedding for Efficiency Improvements
          5. 3.1.2.7.5 Non-Linear Voltage Loop for Transient Reduction
          6. 3.1.2.7.6 Software Phase Locked Loop Methods: SOGI - FLL
    2. 3.2 Testing and Results
      1. 3.2.1 Test Results at Input 120 Vrms, 60 Hz, Output 380-V DC
        1. 3.2.1.1 Startup
        2. 3.2.1.2 Steady State Condition
        3. 3.2.1.3 Transient Test With Step Load Change
          1. 3.2.1.3.1 0% to 50% Load Step Change
          2. 3.2.1.3.2 50% to 100% Load Step Change
          3. 3.2.1.3.3 100% to 50% Load Step Change
          4. 3.2.1.3.4 50% to 100% Load Step Change
      2. 3.2.2 Test Results at Input 230 Vrms, 50 Hz, Output 380 V DC
        1. 3.2.2.1 Startup
        2. 3.2.2.2 Steady State Condition
        3. 3.2.2.3 Transient Test With Step Load Change
          1. 3.2.2.3.1 33% to 100% Load Step Change
          2. 3.2.2.3.2 100% to 33% Load Step Change
      3. 3.2.3 Test Results Graphs
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Software Files
  11. 6Related Documentation
    1. 6.1 Trademarks
  12. 7About the Author
  13. 8Revision History

3.1.1.1 Base Board Settings

The design follows a HSEC control card concept, and any device for which HSEC control card is available from the C2000 MCU product family can be potentially used on this design. The key resources used for controlling the power stage on the MCU are listed in Table 3-1. Figure 3-1 shows the key power stage and connectors on the design board. Table 3-2 lists the key connectors and their functions. To get started:

  1. Make sure no power source is connected to the design.
  2. Insert the control card in the J600 slot.
  3. Connect a 12-V, 1-A DC power supply at TP604. For the ground terminal, use TP606 . Do not power up the supply.
  4. Connect a 5-V, 1-A DC power supply at TP608. For the ground terminal, use TP609. Do not power up the supply.
  5. Turn both the 12-V and 5-V power supply ON. The LED on the control card lights up and indicates the device is powered.
    Note:

    The bias for the MCU is separated from the power stage, which enables safe bring up of the system in this set of instructions. The bias supply design that works with this converter is PMP20396

  6. To connect JTAG, use a USB cable from the control card and connect it into a host computer.
  7. For PFC mode, a single phase AC power supply can be connected to the input J100. Optionally in some labs a DC source may be required to test out the system safely. A resistive load of approximately 500 Ω and 400 W should be connected to the output at J104.
  8. For Inverter mode, A DC power supply can be connected to the input J100. A resistive load of approximately 125 Ω and 200 W should be connected to the output at J104.
  9. Current and voltage probes can be connected to observe the input current, input voltage, and output voltages, as shown in Figure 3-1.
GUID-05F26482-87E7-4465-BF0F-3914047324A1-low.gifFigure 3-1 Board Overview
Table 3-1 Key Controller Peripherals Used for Control of Power Stage on Board
SIGNAL NAMEHSEC PIN NUMBERFUNCTION
PWM-1A49PWM: low-frequency MOSFET leg, high-side switch
PWM-1B51PWM: low-frequency MOSFET leg, low-side switch
PWM-2A53PWM: high frequency GaN leg, high side switch, phase one
PWM-2B55PWM: high-frequency GaN leg, low-side switch, phase one
PWM-3A50PWM: high-frequency GaN leg, high-side switch, phase two
PWM-3B52PWM: high-frequency GaN leg, low-side switch, phase two
PWM-4A54PWM: high-frequency GaN leg, high-side switch, phase three
PWM-4B56PWM: high-frequency GaN leg, low-side switch, phase three
Iac18ADC with CMPSS: AC return current measurement
IL115ADC with CMPSS : inductor current measurement Ph1
IL221ADC with CMPSS : inductor current measurement Ph2
IL325ADC with CMPSS : inductor current measurement Ph3
VL20ADC: AC voltage line
VN17ADC: AC voltage neutral
Vbus24ADC: bus voltage
In Rush Relay57GPIO: used to control the inrush relay
GaN Fault 158GPIO: GaN fault signal phase one
GaN Fault 260GPIO: GaN fault signal phase two
GaN Fault 362GPIO: GaN fault signal phase three
AC Current Sense Gain Change63GPIO: controls the gain stage
Table 3-2 Key Connectors and Function
CONNECTOR NAMEFUNCTION
PFCInverter
J100Input AC voltageOutput AC voltage
J104Output DC bus voltageInput DC bus Voltage
TP604Input bias supply, 12-VDC, 1 A
TP608Input bias supply, 5-VDC, 1 A
TP606/TP609GND
J600HSEC control card connector slot
GUID-851B938C-35A6-4E1C-9B0E-031FCFEE4609-low.gifFigure 3-2 Hardware Setup to Run Software (PFC and Inverter Mode)