TIDUDT0
September 2022
Description
Resources
Features
Applications
5
1
System Description
1.1
Key System Specification
1.1.1
Intel® Stratix® 10 Power Tree Example
1.1.2
Intel® Agilex™ Power Tree Example
1.1.3
Xilinx Versal™ Power Tree Example
1.1.4
Xilinx Virtex-7® Power Tree Example
2
System Overview
2.1
Block Diagram
2.2
Design Considerations
2.3
Highlighted Products
2.3.1
TPS53688
2.3.2
TPS650861
2.3.3
TPSM5D1806
3
Hardware, Software, Testing Requirements, and Test Results
3.1
Hardware Requirements
3.2
Test Setup
3.2.1
TPS53688 Programming Setup
3.2.2
TPS53688 Transient Test Setup
3.2.3
TPS650861 Programming Setup
3.2.4
TPS650861 and TPSM5D1806 Transient Test Setup
3.3
Test Results
3.3.1
Efficiency Results
3.3.2
Transient Results
3.3.2.1
TPS53688 Transient Results
3.3.2.2
TPS650861 Transient Results
3.3.2.3
TPSM5D1806 Transient Results
4
Design and Documentation Support
4.1
Design Files
4.1.1
Schematics
4.1.2
BOM
4.2
Tools and Software
4.3
Documentation Support
4.4
Support Resources
4.5
Trademarks
5
About the Author
Features
Dual-channel DCAP+ controller
6 + 2 phase configuration for core and secondary rails
PMBus and VR13.HC SVID capabilities for dynamic voltage scaling
Six power rails and sequencing from PMIC
Three controllers provides up to 20 A
Three converters provides up to 3 A
Built-in VTT regulator for DDR
Flexible programming allows for custom sequencing and power rail assignment
Compact converter using modules
Configurable module, dual 6-A rails, or single 12-A rail