TIDUDT0 September   2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specification
      1. 1.1.1 Intel® Stratix® 10 Power Tree Example
      2. 1.1.2 Intel® Agilex™ Power Tree Example
      3. 1.1.3 Xilinx Versal™ Power Tree Example
      4. 1.1.4 Xilinx Virtex-7® Power Tree Example
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS53688
      2. 2.3.2 TPS650861
      3. 2.3.3 TPSM5D1806
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
      1. 3.2.1 TPS53688 Programming Setup
      2. 3.2.2 TPS53688 Transient Test Setup
      3. 3.2.3 TPS650861 Programming Setup
      4. 3.2.4 TPS650861 and TPSM5D1806 Transient Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Efficiency Results
      2. 3.3.2 Transient Results
        1. 3.3.2.1 TPS53688 Transient Results
        2. 3.3.2.2 TPS650861 Transient Results
        3. 3.3.2.3 TPSM5D1806 Transient Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  10. 5About the Author

2.3.1 TPS53688

From a performance standpoint the TPS53688 is capable of handling the high-current requirement and low-voltage output that is required for the core current rail for the FPGA. Furthermore the feedback scheme of DCAP+ allows it to have very good transient capabilities to achieve the typical < 1% requirement need on the core rail. Furthermore, its PMBUS and VR13.HC SVID allows it to interface with Intel and Xilinx FPGAs to provide dynamic voltage scaling (DVS) to the core rail to adjust the voltage depending on the mode the FPGA is operating in.