TIDUE53I march   2018  – july 2023 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1  UCC21710
      2. 2.2.2  UCC5320
      3. 2.2.3  TMS320F28379D
      4. 2.2.4  AMC1305M05
      5. 2.2.5  OPA4340
      6. 2.2.6  LM76003
      7. 2.2.7  PTH08080W
      8. 2.2.8  TLV1117
      9. 2.2.9  OPA350
      10. 2.2.10 UCC14240
    3. 2.3 System Design Theory
      1. 2.3.1 Three-Phase T-Type Inverter
        1. 2.3.1.1 Architecture Overview
        2. 2.3.1.2 LCL Filter Design
        3. 2.3.1.3 Inductor Design
        4. 2.3.1.4 SiC MOSFETs Selection
        5. 2.3.1.5 Loss Estimations
        6. 2.3.1.6 Thermal Considerations
      2. 2.3.2 Voltage Sensing
      3. 2.3.3 Current Sensing
      4. 2.3.4 System Power Supplies
        1. 2.3.4.1 Main Input Power Conditioning
        2. 2.3.4.2 Isolated Bias Supplies
      5. 2.3.5 Gate Drivers
        1. 2.3.5.1 1200-V SiC MOSFETs
        2. 2.3.5.2 650-V SiC MOSFETs
        3. 2.3.5.3 Gate Driver Bias Supply
      6. 2.3.6 Control Design
        1. 2.3.6.1 Current Loop Design
        2. 2.3.6.2 PFC DC Bus Voltage Regulation Loop Design
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Test Hardware Required
        2. 3.1.1.2 Microcontroller Resources Used on the Design (TMS320F28379D)
        3. 3.1.1.3 F28377D, F28379D Control-Card Settings
        4. 3.1.1.4 Microcontroller Resources Used on the Design (TMS320F280039C)
      2. 3.1.2 Software
        1. 3.1.2.1 Getting Started With Firmware
          1. 3.1.2.1.1 Opening the CCS project
          2. 3.1.2.1.2 Digital Power SDK Software Architecture
          3. 3.1.2.1.3 Interrupts and Lab Structure
          4. 3.1.2.1.4 Building, Loading and Debugging the Firmware
        2. 3.1.2.2 Protection Scheme
        3. 3.1.2.3 PWM Switching Scheme
        4. 3.1.2.4 ADC Loading
    2. 3.2 Testing and Results
      1. 3.2.1 Lab 1
      2. 3.2.2 Testing Inverter Operation
        1. 3.2.2.1 Lab 2
        2. 3.2.2.2 Lab 3
        3. 3.2.2.3 Lab 4
      3. 3.2.3 Testing PFC Operation
        1. 3.2.3.1 Lab 5
        2. 3.2.3.2 Lab 6
        3. 3.2.3.3 Lab 7
      4. 3.2.4 Test Setup for Efficiency
      5. 3.2.5 Test Results
        1. 3.2.5.1 PFC Mode - 230 VRMS, 400 V L-L
          1. 3.2.5.1.1 PFC Start-up – 230 VRMS, 400 L-L AC Voltage
          2. 3.2.5.1.2 Steady State Results at 230 VRMS, 400 V L-L - PFC Mode
          3. 3.2.5.1.3 Efficiency and THD Results at 220 VRMS, 50 Hz – PFC Mode
          4. 3.2.5.1.4 Transient Test With Step Load Change
        2. 3.2.5.2 PFC Mode - 120 VRMS, 208 V L-L
          1. 3.2.5.2.1 Steady State Results at 120 VRMS, 208 V-L-L - PFC Mode
          2. 3.2.5.2.2 Efficiency and THD Results at 120 VRMS - PFC Mode
        3. 3.2.5.3 Inverter Mode
          1. 3.2.5.3.1 Inverter Closed Loop Results
          2. 3.2.5.3.2 Efficiency and THD Results - Inverter Mode
          3. 3.2.5.3.3 Inverter - Transient Test
      6. 3.2.6 Open Loop Inverter Test Results
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  11. 5Trademarks
  12. 6About the Authors
  13. 7Revision History

3.2.2.2 Lab 3

In this lab the power stage is run in an closed loop on the real HW or HIL platform. Figure 3-10 shows the SW diagram.

GUID-20210222-CA0I-3W9R-QGJS-XDWTHBDHC1PL-low.svgFigure 3-10 Lab 3 Software Diagram

Set the project to Lab 3 by changing the Lab Number in the <settings.h> file, (this will be changed by powerSUITE GUI when using powerSUITE project).

In the user settings.h file some additional options are available, but the following are used for the tests documented in this user guide. 

#if TINV_LAB == 3
#define TINV_TEST_SETUP TINV_TEST_SETUP_RES_LOAD
#define TINV_PROTECTION TINV_PROTECTION_ENABLED
#define TINV_SFRA_TYPE TINV_SFRA_CURRENT
#define TINV_SFRA_AMPLITUDE (float32_t)TINV_SFRA_INJECTION_AMPLITUDE_LEVEL2
#define TINV_POWERFLOW_MODE TINV_INVERTER_MODE
#define TINV_DC_CHECK 0
#define TINV_SPLL_TYPE TINV_SPLL_DDSRF
#endif

Lab 3:

In this check, the SW is run on the hardware, or the HIL platform, or both.

Refer to the hardware test set up section for actual details of the equipment used for configuring the test. At this time, do not supply any HV power to the board.

  • First launch the main.cfg and select lab3 in the project options. The compensator style (PI compensator) and the tuning loop (current loop) will be automatically populated. Now click run compensation designer icon and compensation designer tool will launch, with the model of the current loop plant with parameters specified on the powerSUITE page.
  • The current compensator coefficients used for running the control loop are shown in the following code. The user can modify these coefficients to meet the necessary loop bandwidth and phase margin. The ideal coefficients with resistive load are slightly different than the one used for grid connection because the grid impedance is very low. The compensator design transfer function and response will be as shown in Figure 3-11.
    #define TINV_GI_PI_KP ((float32_t)0.3))
#define TINV_GI_PI_KI ((float32_t)0.0120860479))
  • Once satisfied with the proportional and integral gain values, click on Save COMP. This will save the compensator values into the project. Close the Compensation Designer, and return to the powerSUITE page
  • Build and load the code, use the lab3.js file to populate the watch variables in the CCS window.
  • Turn on the relay by writing a 1 to TINV_allRelaySet. The auxiliary power supply should draw close to 530 mA
  • Set up an appropriate resistive load around 200 Ω to start with although the inverter mode can started at no load as well.
  • Slowly ramp the DC bus voltage 'Vbus' to 800 V.
  • Set the TINV_clearPWMTrip = 1, to clear the PWM trip signal. Now the switching action begins and sinusoidal voltages start appearing at the output. At this point the auxiliary power supply should draw close to 570 mA.
  • As soon as TINV_clearPWMTrip is set, the TINV_closeGiLoop variable is enabled and closed current loop action begins.
  • TINV_idRef_pu is the current command reference and by default it is populated to a value of 0.005 pu at start-up. Slowly vary this to increase the output AC voltage and observe measured current tracks the commanded value.
  • Verify TINV_idRef_pu and TINV_iInv_dq0_pos.d data in the watch window at low before proceeding to close the current loop in Lab 3.
  • Slowly increase id_ref to 0.36 pu at 800-V input voltage to improve output power to 3.7 kW, approximately 1.25 kW per phase. Figure 3-11 shows the power analyzer and scope waveform.
  • Figure 3-11 shows the captured voltage and current waveform of inverter operating in closed current loop at 3.7 kW. Scope signals: Channel 1 - DC link voltage (blue), Channel 2 - AC voltage (light green), Channel 3 - AC current (dark green)
GUID-20210408-CA0I-DTD5-9WFC-RD2R3XQ37TJM-low.pngFigure 3-11 Inverter Closed-Loop Operation
  • SFRA is integrated in the software of this lab to verify the designed compensator provides enough gain and phase margin by measuring on hardware. To run the SFRA keep the project running, and from the cfg page, click on the SFRA icon. SFRA GUI will pop up.
  • Select the options for the device on the SFRA GUI. For example, for F28377D select floating point. Click on Setup Connection. On the pop-up window uncheck the boot on connect option, and select an appropriate COM port. Click OK. Return to the SFRA GUI, and click Connect.
  • The SFRA GUI will connect to the device. A SFRA sweep can now be started by clicking Start Sweep. The complete SFRA sweep will take a few minutes to finish. Activity can be monitored by seeing the progress bar on the SFRA GUI and also checking the flashing of blue LED on the back on the control card that indicates UART activity. Once complete, a graph with the open loop plot will appear, as in Figure 3-12. This verifies that the designed compensator is indeed stable. The SFRA for plant and open loop with the above coefficients is shown in Figure 3-12 and Figure 3-13, respectively. This action verifies the current compensator design. To bring the system to a safe stop, bring the input DC voltage down to zero.
  • The above set of compensation designer coefficients are robust and stable. In case the tracking performance of current against the commanded reference and appears to oscillate, the user can use the following set of coefficients. To change the coefficients, compensation designer tool will have to be relaunched from the power suite page.
    #define TINV_GI_PI_KP ((float32_t)0.144))
#define TINV_GI_PI_KI ((float32_t)0.112))
  • Once satisfied with the proportional and integral gain values, click on Save COMP. This will save the compensator values into the project.
  • The SFRA response of plant and open loop for the inverter in current mode with the new set of coefficients are shown in Figure 3-12 and Figure 3-13, respectively.
GUID-20210408-CA0I-HVLT-6JWP-RGPR8CDCRNVX-low.pngFigure 3-12 Inverter SFRA Plant Response for Current Loop
GUID-20210408-CA0I-ZCGR-SBTT-9QLJ0K1SRXKG-low.pngFigure 3-13 Inverter SFRA Loop Response for Current Loop