TIDUE53I march 2018 – july 2023 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Labs 2, 3, and 4 elaborate the steps for running the power stage in the inverter mode. Lab 2 is the inverter mode of operation in open loop, Lab 3 is the inverter mode of operation with closed current loop. Lab 4 is the grid connected inverter mode of operation and this is checked only under HIL platform and not on the hardware. The high voltage (800 VDC) is applied across terminals J1 and J2. 15-V auxiliary power supply is connected to terminal J33. Three phase star connected resistive load is connected across terminals J3, J4, and J31. J32 is the neutral terminal which is left unconnected to the load.
A check for DC bus overvoltage is added to all Inverter Labs, Lab 1 through Lab 5, using a filtered value of the DC bus voltage. The TINV_filterAndCheckForBusOverVoltage() function runs from ISR1 and checks for DC bus overvoltage condition. Under OV condition this function shuts off all PWM outputs and registers the system operating state as "bus overvoltage state”. Filtered DC bus voltage is calculated from instantaneous sensed DC bus voltage using the averaging function EMAVG. This is all calculated inside ISR1.
The feed-forward and decoupling function is implemented inside ISR1 and added for all Inverter Labs that use a current loop. Therefore, for the inverter mode, this is done (feed-forward and decoupling) in Lab 3 and Lab 4. For this feed-forward and decoupling function filtered DC bus voltage is compared against a user-defined minimum bus voltage to calculate a clamped filtered DC bus voltage. This is also done inside ISR1. This clamped filtered DC bus voltage and the current controller output are finally used to implement the feed-forward and decoupling function.
For SDFM-based current sensing, overcurrent protection (OCP) is also added for all Inverter Labs.