The CLB is responsible for:
- Generating the encoder clock, MA, signal with the CDM bit.
- Monitoring the SPI PICO signal for a response from the encoder.
- Aligning the SPICLK to the incoming response.
- Clocking the SPI to receive the response.
This section describes the design of the CLB tiles using two approaches:
- Visualization of the CLB behavior during each phase of the transaction using
waveforms.
- The CLB tile design including interconnect of the submodules.