TIDUE73A April   2018  – November 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 C2000 Real-Time MCU LaunchPad
      2. 2.2.2 SN65HVD78
      3. 2.2.3 TLV702
      4. 2.2.4 TPS22918-Q1
    3. 2.3 Design Considerations
      1. 2.3.1 BiSS-C Protocol
        1. 2.3.1.1 Line Delay Compensation
        2. 2.3.1.2 Processing Time Request by Encoder
        3. 2.3.1.3 Control Communication
      2. 2.3.2 C2000 BiSS-C Encoder Interface Overview
      3. 2.3.3 TIDM-1010 Board Implementation
      4. 2.3.4 MCU Resource Requirements
        1. 2.3.4.1 Input, Output Signals, and CLB Tiles
      5. 2.3.5 CLB BiSS-C Implementation Details
        1. 2.3.5.1 Transaction Waveforms
        2. 2.3.5.2 FRAME_STATE Generation
        3. 2.3.5.3 CLB_SPI_CLOCK Generation
        4. 2.3.5.4 ENCODER_CLOCK (MA) Generation
      6. 2.3.6 PM BiSS-C Interface Library
        1. 2.3.6.1 PM BiSS-C Library Functions
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1 TIDM-1010 Jumper Configuration
    2. 3.2 Software
      1. 3.2.1 C2000 Driver Library (DriverLib)
      2. 3.2.2 C2000 SysConfig
      3. 3.2.3 C2000 Configurable Logic Block Tool
      4. 3.2.4 Installing Code Composer Studio™ and C2000WARE-MOTORCONTROL-SDK
      5. 3.2.5 Locating the Reference Software
    3. 3.3 Testing and Results
      1. 3.3.1 Hardware Configuration
      2. 3.3.2 Building and Loading Project
      3. 3.3.3 Running Example Code
      4. 3.3.4 Encoder Test
      5. 3.3.5 Benchmarks
      6. 3.3.6 Troubleshooting
  10. 4Design Files
  11. 5Software Files
  12. 6Related Documentation
    1.     Trademarks
  13. 7Terminology
  14. 8About the Authors
  15. 9Revision History

2.3.1 BiSS-C Protocol

The BiSS-C interface specification describes a serial interface protocol to communicate with encoders and other sensors. BiSS-C allows the simultaneous transmission of position data and the control data over the same line. The interface is similar to the serial synchronous interface (SSI) protocol where the data transmission is synchronized with the controller clock signal.

Table 2-1 SSI Compared to BiSS-C
SSI (Serial Synchronous Interface) BiSS-C
2Mbits / s Up to 10Mbits / s on 10 meter cable
N/A Cable length propagation compensation
Differential twisted pair cable (RS-422/485) Differential twisted pair cable (RS-422/485)
Unidirectional. Only supports data transmission from encoder to controller. Often used uni-directionally like SSI. Also supports bidirectional data transmission enabling the encoder configuration can be controlled by the drive.
Supports a simple parity check Robust error checking by Cyclic Redundancy Check (CRC)
N/A Encoder can request additional processing time
Point-to-point topology only Typically point-to-point, but the protocol also supports daisy chained encoders. The C2000 design discussed in this document implements a point-to-point topology.
Note: This document describes some important concepts of the BiSS-C frame and control communication. For the detailed specifications, see BiSS User Society and Internet Platform

Though position encoders typically provide the feedback-position data of motors, this encoder allows closed-loop control of motors. This design implements the BiSS-C interface for point-to-point communication. In the point-to-point configuration, only one such encoder is interfaced to by the controller or drive.

In the BiSS-C protocol, the controller provides a clock (MA) to the encoder and then the encoder sends data back to the controller (SL). The communication data consists of single-cycle data (SCD) and control data (CD).

  • SCD is the primary data transmitted from the encoder to the controller and is updated every BiSS cycle. The SCD includes the absolute position, error bit, warning bit and a CRC check. The absolute position can be single-turn only (one revolution) or can include both single-turn and multi-turn (number of revolutions) data.
  • CD enables the controller to write and read encoder registers. The controller sends one control data bit (CDM) to the encoder, and the encoder returns one control data bit (CDS) back to the controller each cycle.
TIDM-1010 BiSS-C Frame Figure 2-2 BiSS-C Frame

Figure 2-2 shows an example BiSS frame. In the reset state, both the MA and SL lines are active high. The controller starts the frame by sending the clock over the MA line. On the second rising edge of the MA clock, the encoder responds with a low signal to acknowledge (ACK) the BiSS frame. For the next MA clock cycle, a start bit is asserted by the encoder. Following START, the encoder sends a control data (CDS) bit, which is the response to the control CDM bit sent in the previous frame.

After the CDS bit, the encoder sends the position data starting with the most significant bits (MSBs). The position data is followed by an error bit (nE) and a warning bit (nW). The encoder then sends the cyclic redundancy check (CRC) bits with the MSB first. The CRC is sent inverted by the encoder over the SL line.

After sending all the bits, the encoder goes into the BiSS time-out state driving SL to a low signal level. SL then goes high when the encoder is ready for the next transmission or expiration of the BiSS time-out. The inverted state of the MA clock line during the BiSS time-out is the CDM bit for control communication. One control data bit is sent in each BiSS frame by the controller and one bit is sent back by the encoder.

Note: An encoder has an SLI (input) and an SLO (output) signal. In the point-to-point configuration, the SLO signal is directly connected to the SL of the controller.