TIDUE73A April   2018  – November 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 C2000 Real-Time MCU LaunchPad
      2. 2.2.2 SN65HVD78
      3. 2.2.3 TLV702
      4. 2.2.4 TPS22918-Q1
    3. 2.3 Design Considerations
      1. 2.3.1 BiSS-C Protocol
        1. 2.3.1.1 Line Delay Compensation
        2. 2.3.1.2 Processing Time Request by Encoder
        3. 2.3.1.3 Control Communication
      2. 2.3.2 C2000 BiSS-C Encoder Interface Overview
      3. 2.3.3 TIDM-1010 Board Implementation
      4. 2.3.4 MCU Resource Requirements
        1. 2.3.4.1 Input, Output Signals, and CLB Tiles
      5. 2.3.5 CLB BiSS-C Implementation Details
        1. 2.3.5.1 Transaction Waveforms
        2. 2.3.5.2 FRAME_STATE Generation
        3. 2.3.5.3 CLB_SPI_CLOCK Generation
        4. 2.3.5.4 ENCODER_CLOCK (MA) Generation
      6. 2.3.6 PM BiSS-C Interface Library
        1. 2.3.6.1 PM BiSS-C Library Functions
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1 TIDM-1010 Jumper Configuration
    2. 3.2 Software
      1. 3.2.1 C2000 Driver Library (DriverLib)
      2. 3.2.2 C2000 SysConfig
      3. 3.2.3 C2000 Configurable Logic Block Tool
      4. 3.2.4 Installing Code Composer Studio™ and C2000WARE-MOTORCONTROL-SDK
      5. 3.2.5 Locating the Reference Software
    3. 3.3 Testing and Results
      1. 3.3.1 Hardware Configuration
      2. 3.3.2 Building and Loading Project
      3. 3.3.3 Running Example Code
      4. 3.3.4 Encoder Test
      5. 3.3.5 Benchmarks
      6. 3.3.6 Troubleshooting
  10. 4Design Files
  11. 5Software Files
  12. 6Related Documentation
    1.     Trademarks
  13. 7Terminology
  14. 8About the Authors
  15. 9Revision History

2.3.5.1 Transaction Waveforms

When implementing a CLB design, first visualizing the required CLB behavior using waveforms can be helpful. To do this, first consider an an example transaction. Recall a BiSS-C transaction consists of the MA signal plus the encoder's response. A transmission can be broken up into FRAME_STATEs as shown in Figure 2-11. The first step is to map each element of the transaction to a CLB submodule. An example mapping is shown in Table 2-4.

Table 2-4 BiSS-C Transaction to CLB Mapping
Transaction Behavior CLB Mapping
Track the FRAME_STATE Finite State Machine (FSM): transitions to a new state given the previous state and current inputs.
Generate two clock signal of a specific width: one for MA and one for the SPI clock. For each signal, this requirement maps to a COUNTER. Leverage the match values to generate the timing for the rising/falling edges. A LUT (Lookup Table) then generates the actual edges based on this timing.
Transmit a specific number of clock pulses for MA and for SPI clock. For each clock, this maps to a COUNTER. On the edge of the clock the COUNTER increments and a MATCH indicates when the number is reached.
Align the SPI clock with the encoder's response The COUNTER generating the SPI clock can be configured such that the edge transition is properly aligned with the encoder's response.
Only allow the SPI to be clocked when receiving the encoder's response A LUT blocks the clock when the clock is not needed
During the BiSS timeout, hold the MA signal high or low (CDM bit) Using GPREG input, the C28 can tell the CLB if the CDM must be high or low. This combined with a LUT then hold the value on MA after the specific number of clocks have been transmitted.
Control the TxEN For BiSS-C, the TxEN is held low. The CLB output LUT can apply a constant "0" to an output.
Tell the CLB to start the transaction by sending MA The C28x configures the COUNTER and SPI for the transaction. The CLB GPREG allows the C28x CPU to directly change a CLB input to start a transaction.
TIDM-1010 BiSS-C Single Cycle Data Transaction Example Figure 2-11 BiSS-C Single Cycle Data Transaction Example

The next step is visualization of the specific submodule behavior. Start with a quick sketch and then add additional detail as the design develops. Figure 2-12 shows an example waveform that was generated using the CLB SystemC simulation model with a custom input as the encoder's response. While Figure 2-12 was generated by the actual design, the figure's detail is similar to a preliminary sketch.

TIDM-1010 CLB Communication Waveform Figure 2-12 CLB Communication Waveform

Markers 1 - 4 in Figure 2-12 are used in the following sections to describe specific behavior of the design with respect to that marker. The markers are:

  1. Transition from IDLE to TRANSMIT_MA
  2. Transition from TRANSMIT_MA to TRANSMIT_MA_AND_RECEIVE_SL
  3. During TRANSMIT_MA_AND_RECEIVE_SL
  4. Transition to RECEIVE_SL

During IDLE there is no activity on the interface. The C28x must initiaite the transaction by:

  • Configureing the CLB and SPI
  • Pulling the START_OPERATION signal high through the CLB Tile's GPREG register. GPREG is the CLB's general purpose register which allows the C28x to directly control a tile's inputs.

Refer to: Figure 2-12, marker (1).

START_OPERATION remains high for one CLB_CLOCK because the CLB's rising edge filter is enabled for that input. At marker (1) the main state machine (FSM1 on Tile4) responds by moving FRAME_STATE from IDLE to the TRANSMIT_MA state.

During TRANSMIT_MA:the encoder interface sends the MA signal to the encoder. This signal is a clock with a specific duty cycle and defined number of clock cycles. The number of cycles depends on the resolution of the encoder. While clocking MA, the CLB monitors the SL line for an encoder response.

Refer to: Figure 2-12, marker (2).

To detect the encoder's response, the CLB monitors SL for a rising edge. The rising edge corresponds to the START bit after the ACK. The time required to detect the response can be any number of clocks and depends on the state of the encoder and the cable length. In addition, if the encoder requires extra time to respond, the ACK state is extended.

When the encoder's START bit is detected, the FRAME_STATE transitions to send MA and receive SL.

Refer to: Figure 2-12, marker (3).

The CLB starts clocking the SPI peripheral to receive the response.

  • The CLB aligns CLB_SPI_CLOCK to the response. The response is sampled on the rising-edge of the CLB generated clock.
  • The CLB_SPI_CLOCK is connected to SPI_CLK_IN by directly overriding the input to the peripheral.
  • A counter tracks the number of SPI clocks generated. Match1 of this counter indicates when the required SPI clocks have been sent. Additional SPI clocks, beyond what is required by the response length, are sometimes needed to fill the FIFO of the SPI to the FIFO interrupt level.

Refer to: Figure 2-12, marker (4).