TIDUE73A April   2018  – November 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 C2000 Real-Time MCU LaunchPad
      2. 2.2.2 SN65HVD78
      3. 2.2.3 TLV702
      4. 2.2.4 TPS22918-Q1
    3. 2.3 Design Considerations
      1. 2.3.1 BiSS-C Protocol
        1. 2.3.1.1 Line Delay Compensation
        2. 2.3.1.2 Processing Time Request by Encoder
        3. 2.3.1.3 Control Communication
      2. 2.3.2 C2000 BiSS-C Encoder Interface Overview
      3. 2.3.3 TIDM-1010 Board Implementation
      4. 2.3.4 MCU Resource Requirements
        1. 2.3.4.1 Input, Output Signals, and CLB Tiles
      5. 2.3.5 CLB BiSS-C Implementation Details
        1. 2.3.5.1 Transaction Waveforms
        2. 2.3.5.2 FRAME_STATE Generation
        3. 2.3.5.3 CLB_SPI_CLOCK Generation
        4. 2.3.5.4 ENCODER_CLOCK (MA) Generation
      6. 2.3.6 PM BiSS-C Interface Library
        1. 2.3.6.1 PM BiSS-C Library Functions
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1 TIDM-1010 Jumper Configuration
    2. 3.2 Software
      1. 3.2.1 C2000 Driver Library (DriverLib)
      2. 3.2.2 C2000 SysConfig
      3. 3.2.3 C2000 Configurable Logic Block Tool
      4. 3.2.4 Installing Code Composer Studio™ and C2000WARE-MOTORCONTROL-SDK
      5. 3.2.5 Locating the Reference Software
    3. 3.3 Testing and Results
      1. 3.3.1 Hardware Configuration
      2. 3.3.2 Building and Loading Project
      3. 3.3.3 Running Example Code
      4. 3.3.4 Encoder Test
      5. 3.3.5 Benchmarks
      6. 3.3.6 Troubleshooting
  10. 4Design Files
  11. 5Software Files
  12. 6Related Documentation
    1.     Trademarks
  13. 7Terminology
  14. 8About the Authors
  15. 9Revision History

2.3.2 C2000 BiSS-C Encoder Interface Overview

Communication over a BiSS-C encoder interface is primarily achieved by the following components:

  • CPU (C28x)
    • Configures the device, CLB and SPI
    • Initializes CLB counters to generate the proper the MA clock frequency and clock counts for the encoder's resolution
    • Packs and unpacks data
    • Calculates the single-cycle-data CRC and control frame CRC
    • Compares calculated CRC with received CRC
  • Configurable logic block (CLB)
    • Sends the MA clock and CDM bit
    • Monitors the SPI PICO signal for the encoder's response. Controls the SPI clock to read the response
    • Measures, and compensates for, cable propagation delay as required by the interface
  • Serial peripheral interface (SPI)
    • Receives the encoder's response
  • Device interconnects (XBARs, CLB XBARS)
    • Routes signals into and out of the CLB and the device
  • External interface block
    • TIDM-1010 board with RS-485 differential line driver
TIDM-1010 Encoder Interface Implementation Block Diagram Figure 2-7 Encoder Interface Implementation Block Diagram
Note: On the F2837xD / F2837xS / F28007 devices the CLB can not override the SPI input signals directly. The TIDM-1010 hardware can route the CLB generated SPI clock back to the peripheral clock input pin and tie the SPI PDE pin to ground. Refer to the TIDM-1010 schematics for more information.

The remainder of this section describes the following aspects of the design:

  • The TIDM-1010 hardware
  • C2000 MCU resources including the CLB
  • C2000 software used by the encoder interface