TIDUEB8C July   2018  – March 2021 TPS274160

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 LM5165
      2. 2.2.2 TLC59282
      3. 2.2.3 TPS4H160-Q1
      4. 2.2.4 INA253
      5. 2.2.5 TIOL111
    3. 2.3 System Design Theory
      1. 2.3.1 IO-Link PHY
      2. 2.3.2 Current Sink
      3. 2.3.3 Power Supply for L+
      4. 2.3.4 Power Supply
      5. 2.3.5 Pinouts
    4. 2.4 Software Frame Handler
      1. 2.4.1 PRU-ICSS IO-Link Frame-Handler
        1. 2.4.1.1 Performance Advantages and Benefits
        2. 2.4.1.2 Principle of Operation
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
      2. 3.1.2 Software
    2. 3.2 Testing and Results
      1. 3.2.1 Test Setup
      2. 3.2.2 Test Results
        1. 3.2.2.1 IO-Link Wake-Up Pulse
        2. 3.2.2.2 L+ Turnon Behavior
        3. 3.2.2.3 Current Sink on CQ
        4. 3.2.2.4 Residue Voltage
        5. 3.2.2.5 IO-Link Physical Layer Test Summary
        6. 3.2.2.6 Current Sense on Each Port
        7. 3.2.2.7 TPS4H160 Thermal Behavior
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Software Files
  11. 6Related Documentation
    1. 6.1 Trademarks
  12. 7About the Author
  13. 8Revision History

3.2.2.2 L+ Turnon Behavior

The turn on of the L+ line is tested by applying a capacitor of 1000 µF, shorted by 150-Ω resistive load. The IO-Link master has to deliver at least 400 mA for 50 ms to pass this test. This load simulates a IO-Link device with a large input capacitor and a static load.

GUID-36C8254D-DB11-4FF0-BE05-AC63E6F1F18B-low.pngFigure 3-6 Testcase TCM_PHYL_INTF_ISIRM: – Power-On Supply Current Capability

Figure 3-6 shows the test results. Channel 2 shows the voltage on the L+ line, channel 4 shows the current on L+. As the load is capacitive and resistive, at the beginning the current is limited to 600 mA by the high-side switch, for about 70 ms. After this time, the resistive load remains and draws a current of 200 mA. Since this energy is more than the necessary 400 mA × 50 ms = 20 mA, this test is passed.

However, different IO-Link master implementations behave very different in this test.