TIDUEE5A October   2018  – May 2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagrams
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 DLP3030-Q1
      2. 2.3.2 DLPC120-Q1
      3. 2.3.3 TMS320F28023
    4. 2.4 System Design Theory
      1. 2.4.1 Head-up Display Parameter Design and Tradeoffs
        1. 2.4.1.1 Field of View and Eyebox
        2. 2.4.1.2 Resolution
        3. 2.4.1.3 Virtual Image Distance
      2. 2.4.2 Picture Generation Unit Design Decisions
        1. 2.4.2.1 Etendue Efficiency Match
        2. 2.4.2.2 Aperture Size: Selecting f/# of Optics
        3. 2.4.2.3 Thermal Design
        4. 2.4.2.4 LED Selection Summary
      3. 2.4.3 Design Summary
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
      2. 3.1.2 Software
    2. 3.2 Testing and Results
      1. 3.2.1 Test Setup
      2. 3.2.2 Test Results
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Cadence Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Software Files
  11. 6Related Documentation
    1. 6.1 Trademarks
  12. 7Terminology
  13. 8Revision History

4.3 PCB Layout Recommendations

Refer to DLPC120-Q1 data sheet for specific PCB layout and routing guidelines. For specific DMD PCB guidelines, use the following:

  • VCC should have at least one 2.2-µF and four 0.1-µF capacitors evenly distributed among the thirteen VCC pins.
  • A 0.1-µF, X7R rated capacitor should be placed near every pin for the VREF, VBIAS, VRSET, and VOFF.