TIDUEJ8C January   2019  – May 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 MSPM0G1506
      2. 2.3.2 LMG2100R044
      3. 2.3.3 INA241
      4. 2.3.4 TPSM365
      5. 2.3.5 TMP303
    4. 2.4 System Design Theory
      1. 2.4.1 MPPT Operation
      2. 2.4.2 Buck Converter
        1. 2.4.2.1 Output Inductance
        2. 2.4.2.2 Input Capacitance
      3. 2.4.3 Current Sense Amplifier
        1. 2.4.3.1 Shunt Resistor Selection
        2. 2.4.3.2 Current Measurement Resolution
        3. 2.4.3.3 Shunt Resistor Power Dissipation
      4. 2.4.4 Switching Regulator
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 TIDA-010042
        2. 3.1.1.2 ITECH-IT6724H
        3. 3.1.1.3 Chroma, 63107A
      2. 3.1.2 Software Flow
    2. 3.2 Testing and Results
      1. 3.2.1 Test Setup
      2. 3.2.2 Test Results
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Loop Inductances
      2. 4.3.2 Current Sense Amplifiers
      3. 4.3.3 Trace Widths
      4. 4.3.4 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
    7. 4.7 Software Files
  11. 5Related Documentation
    1. 5.1 Trademarks
    2. 5.2 Support Resources
  12. 6About the Author
  13. 7Revision History

TIDA-010042

Figure 3-1 and Figure 3-2 show the full design boards, with the bare PCB measuring at 83mm × 82mm.

TIDA-010042 TIDA-010042 Top ViewFigure 3-1 TIDA-010042 Top View
TIDA-010042 TIDA-010042 Bottom ViewFigure 3-2 TIDA-010042 Bottom View

Table 3-1 breaks out the various headers and their associated pin connections.

J1, J2, and J3 are the PV panel, battery, and load connections, respectively.

J4 is used for XDS110 debugger.

J5 can be configured to communicate with power line communication (PLC) board in the future.

TIDA-010042 TIDA-010042 Board HeadersFigure 3-3 TIDA-010042 Board Headers
Table 3-1 Headers Connections
DESIGNATORPIN NUMBERSIGNAL
J1 – PV panel connection1Negative panel (P–) terminal
2Positive panel (P+) terminal
J2 – battery connection1Positive battery (B+) terminal
2Negative battery (B–) terminal
J3 – load connection1Negative load (L–) terminal
2Positive load (L+) terminal
J4 – programming header1XDS110 Programmer voltage
2XDS110 SWDIO
3GROUND
4XDS110 SWCLK
5GROUND
6FLOAT
7GROUND
8FLOAT
9GROUND
10XDS110 RST
J5 – PLC connection1PLC1
2PLC2
3PLC3
4PLC4
5PLC5
6PLC6
7PLC7
8PLC8
9PLC9
10PLC10
11UART_TX
12POWER 3.3V
13UART_RX
14Buzzer output
15GROUND
16GROUND