TIDUEJ8C January   2019  – May 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 MSPM0G1506
      2. 2.3.2 LMG2100R044
      3. 2.3.3 INA241
      4. 2.3.4 TPSM365
      5. 2.3.5 TMP303
    4. 2.4 System Design Theory
      1. 2.4.1 MPPT Operation
      2. 2.4.2 Buck Converter
        1. 2.4.2.1 Output Inductance
        2. 2.4.2.2 Input Capacitance
      3. 2.4.3 Current Sense Amplifier
        1. 2.4.3.1 Shunt Resistor Selection
        2. 2.4.3.2 Current Measurement Resolution
        3. 2.4.3.3 Shunt Resistor Power Dissipation
      4. 2.4.4 Switching Regulator
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 TIDA-010042
        2. 3.1.1.2 ITECH-IT6724H
        3. 3.1.1.3 Chroma, 63107A
      2. 3.1.2 Software Flow
    2. 3.2 Testing and Results
      1. 3.2.1 Test Setup
      2. 3.2.2 Test Results
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Loop Inductances
      2. 4.3.2 Current Sense Amplifiers
      3. 4.3.3 Trace Widths
      4. 4.3.4 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
    7. 4.7 Software Files
  11. 5Related Documentation
    1. 5.1 Trademarks
    2. 5.2 Support Resources
  12. 6About the Author
  13. 7Revision History

2.3.2 LMG2100R044

TIDA-010042 LMG2100 Functional Block DiagramFigure 2-3 LMG2100 Functional Block Diagram

The LMG2100R044 device is an 80-V continuous, 100V pulsed, 35A half-bridge power stage, with integrated gate-driver and enhancement-mode Gallium Nitride (GaN) FETs, 4.4mΩ RDS(on).

  • 5V external bias power supply
  • Near zero reverse recovery
  • Very small input capacitance CISS and output capacitance COSS
  • High slew rate switching with low ringing
  • Internal bootstrap supply voltage clamping to prevent GaN FET Overdrive
  • Excellent propagation delay (29.5ns typical) and matching (2ns typical)
  • Low power consumption
  • Exposed top QFN package for top-side cooling
  • Package optimized for easy PCB layout
  • 5.5mm × 4.5mm × 0.89mm lead-free package

The device extends advantages of discrete GaN FETs by offering a more user-friendly interface. This device is an excellent choice for applications requiring high-frequency, high-efficiency operation in a small form factor.

The LMG2100R044, half-bridge, GaN power stage with highly integrated high-side and low-side gate drivers, which includes built-in UVLO protection circuitry and an overvoltage clamp circuitry. The clamp circuitry limits the bootstrap refresh operation to make sure that the high-side gate driver overdrive does not exceed 5.4V. The device integrates two, 4.4mΩ GaN FETs in a half-bridge configuration. The device can be used in many isolated and non-isolated topologies allowing very simple integration. HI and LI can be independently controlled to minimize the third quadrant conduction of the low-side FET for hard switched buck converters. The package is designed to minimize the loop inductance while keeping the PCB design simple. TI recommends a size of 0402 to minimize trace length to the pin. Place the bypass and bootstrap capacitors as close as possible to the device to minimize parasitic inductance. The drive strengths for turn on and turn off are optimized to provide high-voltage slew rates without causing any excessive ringing on the gate or power loop.