TIDUEM7A April   2019  – February 2021

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 End Equipment
      1. 1.1.1 Electricity Meter
    2. 1.2 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 ADS131M04
      2. 2.2.2 TPS7A78
      3. 2.2.3 MSP432P4111
      4. 2.2.4 TPS3840
      5. 2.2.5 THVD1500
      6. 2.2.6 ISO7731B
      7. 2.2.7 TRS3232E
      8. 2.2.8 TPS709
      9. 2.2.9 ISO7720
    3. 2.3 Design Considerations
      1. 2.3.1 Design Hardware Implementation
        1. 2.3.1.1 TPS7A78 Cap-Drop Supply
        2. 2.3.1.2 TPS3840 SVS
        3. 2.3.1.3 Analog Inputs
          1. 2.3.1.3.1 Voltage Measurement Analog Front End
          2. 2.3.1.3.2 Current Measurement Analog Front End
      2. 2.3.2 Current-Detection Mode
        1. 2.3.2.1 ADS131M04 Current-Detection Procedure
        2. 2.3.2.2 Using an MCU to Trigger Current-Detection Mode
          1. 2.3.2.2.1 Using a Timer to Trigger Current-Detection Mode Regularly
          2. 2.3.2.2.2 MCU Procedure for Entering and Exiting Current-Detection Mode
        3. 2.3.2.3 How to Implement Software for Metrology Testing
          1. 2.3.2.3.1 Setup
            1. 2.3.2.3.1.1 Clock
            2. 2.3.2.3.1.2 Port Map
            3. 2.3.2.3.1.3 UART Setup for GUI Communication
            4. 2.3.2.3.1.4 Real-Time Clock (RTC)
            5. 2.3.2.3.1.5 LCD Controller
            6. 2.3.2.3.1.6 Direct Memory Access (DMA)
            7. 2.3.2.3.1.7 ADC Setup
          2. 2.3.2.3.2 Foreground Process
            1. 2.3.2.3.2.1 Formulas
          3. 2.3.2.3.3 Background Process
            1. 2.3.2.3.3.1 per_sample_dsp()
              1. 2.3.2.3.3.1.1 Voltage and Current Signals
              2. 2.3.2.3.3.1.2 Frequency Measurement and Cycle Tracking
            2. 2.3.2.3.3.2 LED Pulse Generation
            3. 2.3.2.3.3.3 Phase Compensation
    4. 2.4 Hardware, Software, Testing Requirements, and Test Results
      1. 2.4.1 Required Hardware and Software
        1. 2.4.1.1 Cautions and Warnings
        2. 2.4.1.2 Hardware
          1. 2.4.1.2.1 Connections to the Test Setup
          2. 2.4.1.2.2 Power Supply Options and Jumper Settings
        3. 2.4.1.3 Software
      2. 2.4.2 Testing and Results
        1. 2.4.2.1 Test Setup
          1. 2.4.2.1.1 SVS and Cap-Drop Functionality Testing
          2. 2.4.2.1.2 Electricity Meter Metrology Accuracy Testing
          3. 2.4.2.1.3 Current-Detection Mode Testing
          4. 2.4.2.1.4 Viewing Metrology Readings and Calibration
            1. 2.4.2.1.4.1 Viewing Results From LCD
            2. 2.4.2.1.4.2 Calibrating and Viewing Results From PC
              1. 2.4.2.1.4.2.1 Viewing Results
              2. 2.4.2.1.4.2.2 Calibration
                1. 2.4.2.1.4.2.2.1 Gain Calibration
                  1. 4.2.1.4.2.2.1.1 Voltage and Current Gain Calibration
                  2. 4.2.1.4.2.2.1.2 Active Power Gain Calibration
                2. 2.4.2.1.4.2.2.2 Offset Calibration
                3. 2.4.2.1.4.2.2.3 Phase Calibration
        2. 2.4.2.2 Test Results
          1. 2.4.2.2.1 SVS and TPS7A78 Functionality Testing Results
          2. 2.4.2.2.2 Electricity Meter Metrology Accuracy Results
          3. 2.4.2.2.3 Current-Detection Mode Results
  8. 3Design Files
    1. 3.1 Schematics
    2. 3.2 Bill of Materials
    3. 3.3 PCB Layout Recommendations
      1. 3.3.1 Layout Prints
    4. 3.4 Altium Project
    5. 3.5 Gerber Files
    6. 3.6 Assembly Drawings
  9. 4Related Documentation
    1. 4.1 Trademarks
  10. 5About the Author
  11. 6Revision History
2.3.2.3.1.7 ADC Setup

Figure 2-13 shows the process used to initialize the ADS131M04. This process is followed when the ADS131M04 device is first setup after the MSP432 MCU resets as well as each time calibration is performed.

GUID-6FFBA2B2-9975-4B33-B7E7-DB098F5FB3AE-low.gifFigure 2-13 ADC Initialization and Synchronization Process

Before setting up the ADS131M04 device, the test code disables the ADS131M04 modulator clock to prevent the ADS131M04 from generating new samples while trying to set it up. The code disables the modulator clock by disabling the SMCLK output of the MSP432 MCU, which is fed to the CLKIN pin of the ADS131M04 device. Disabling the SMCLK output only needs to be done after calibration and not after an MSP432 MCU reset event since the SMCLK clock output is automatically not output after the MSP432 MCU resets.

After the SMCLK output is disabled, the EUSCIB0 SPI module of the MSP432 MCU is configured for communication to the ADS131M04 device. The EUSCIB0 SPI module is specifically configured as a master device that uses 3-wire mode (the chip select signal is manually asserted high and low in the test software instead of using the chip select feature of the SPI module) and has an 8.192-MHz SPI clock that is derived from the 8.192-MHz SMCLK clock. After the SPI is setup, all interrupts are disabled and a reset command is sent from the MSP432 MCU to the ADS131M04 via SPI. Interrupts are then re-enabled and the MSP432 MCU sends commands to the ADS131M04 to configure its registers.

At this point, note that the modulation clock is not output by the MSP432 MCU, which means that sampling is not started yet. By sending commands to the ADS131M04 to initialize the ADS131M04 registers, the ADS131M04 is configured for the following:

  • MODE register settings: 16-bit CCITT CRC used, 24-bit length for each word in the ADS131M04 packet, DRDY signal asserted on most lagging enabled channel, DRDY asserted high when conversion value is not available, DRDY asserted low when conversion values are ready
  • GAIN1 register settings: PGA gain of 1 used for voltage channel and CT channel; PGA gain of 32 used for shunt channel (assuming 200-µΩ shunts)
  • CFG register settings: CD=1 (current-detection mode enabled), CD_ALLCH=0(MCU triggered based on if any enabled channel detects tamper current), CD_NUM(current-detect number of threshold exceeds to trigger detect)=8, CD_LEN(current-detect measurement length in conversion periods)=256
  • CHn_CNG register settings (where n is the channel number) : Channels 0, 1, and 2 inputs connected to external ADC pins and channel phase delay set to 0 for channels 0, 1, and 2 (note that software phase compensation is used instead of ADS131M04 hardware phase compensation); the channel 3 config register is not modified since channel 3 is not used for this configuration.
  • CLOCK register settings: 512 OSR, all channels enabled, and high-resolution modulator power mode
  • CD_THRSHLD=80000
  • CHn_OCAL register settings (where n is the channel number) = measured channel DC offset (for only current channels)

Before initializing the registers, an estimate of the ADC offset(in ADC units) for each current channel is determined using the PC GUI. The offset calibration registers for the current channels are then updated with the corresponding offsets to subtract out most of the ADC offset from both current channels. This offset calibration is done to have better matching between the line and neutral ADC channels, which has significantly different ADC offsets due to different gains being used on these channels. Having better matching between the line and neutral ADC channels enables the line and neutral current channels to cause a trigger in current-detection mode when nearly the same neutral and line current is applied to the meter. For even more precise matching between the line and neutral currents needed to trigger current-detection mode, the gain registers on the two current channels can be modified as well; however, for this design, good enough ADC matching was obtained without modifying the gain calibration registers of the ADS131M04 device so these registers were left unmodified.

In this design, CD_LEN=256, which allows current-detection to be performed over more than 4 Mains cycles of ADC samples. The CD_LEN time determines the maximum time spent in current-detection mode before the device returns to standby mode. Decreasing the value of CD_LEN decreases the time in current-detection mode, which reduces the average current consumption drawn from the ADS131M04 device after an AC supply failure.

After the ADS131M04 registers are properly initialized, the MSP432 MCU is configured to generate a port interrupt whenever a falling edge occurs on the DRDY pin, which indicates that the ADS131M04 device has new samples available. Next, the MSP432 MCU outputs the SMCLK clock to the ADS131M04, which starts the voltage and current sampling.

The ADS131M04 modulator clock is derived from the clock fed to its CLKIN pin, which is output from the SMCLK output of the MSP432 MCU. The clock fed to the CLKIN pin of the ADS131M04 device is internally divided by two, to generate the ADS131M04 modulator clock. The sampling frequency of the ADS131M04 is therefore defined as:

Equation 7. fs = fM / OSR = fCLKIN / (2 × OSR)

where

  • fs is the sampling rate
  • fM is the modulator clock frequency
  • fCLKIN is the clock fed to the ADS131M04 CLKIN pin
  • OSR is the selected oversampling ratio

In this design, the SMCLK clock of the MSP432 MCU that is fed to the ADS131M04 CLKIN pin has a frequency of 8.192 MHz. The oversampling ratio is selected to be 512. As a result, the ADS131M04 modulator clock is set to 4.096 MHz and the sample rate is set to 8000 samples per second.

In this design, the following ADS131M04 channel mappings are used:

  • AIN0P and AIN0N ADS131M04 ADC channel pins → Voltage
  • AIN1N and AIN1P ADS131M04 ADC channel pins →Shunt Current (This is the primary current channel; this can measure either the neutral or line current)
  • AIN2P and AIN2N ADS131M04 ADC channel pins →CT Current(This is the secondary current channel; this can measure either the line or neutral current)
  • AIN3P and AIN3N ADS131M04 ADC channel pins → Not used in design