TIDUEM7A April   2019  – February 2021

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 End Equipment
      1. 1.1.1 Electricity Meter
    2. 1.2 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 ADS131M04
      2. 2.2.2 TPS7A78
      3. 2.2.3 MSP432P4111
      4. 2.2.4 TPS3840
      5. 2.2.5 THVD1500
      6. 2.2.6 ISO7731B
      7. 2.2.7 TRS3232E
      8. 2.2.8 TPS709
      9. 2.2.9 ISO7720
    3. 2.3 Design Considerations
      1. 2.3.1 Design Hardware Implementation
        1. 2.3.1.1 TPS7A78 Cap-Drop Supply
        2. 2.3.1.2 TPS3840 SVS
        3. 2.3.1.3 Analog Inputs
          1. 2.3.1.3.1 Voltage Measurement Analog Front End
          2. 2.3.1.3.2 Current Measurement Analog Front End
      2. 2.3.2 Current-Detection Mode
        1. 2.3.2.1 ADS131M04 Current-Detection Procedure
        2. 2.3.2.2 Using an MCU to Trigger Current-Detection Mode
          1. 2.3.2.2.1 Using a Timer to Trigger Current-Detection Mode Regularly
          2. 2.3.2.2.2 MCU Procedure for Entering and Exiting Current-Detection Mode
        3. 2.3.2.3 How to Implement Software for Metrology Testing
          1. 2.3.2.3.1 Setup
            1. 2.3.2.3.1.1 Clock
            2. 2.3.2.3.1.2 Port Map
            3. 2.3.2.3.1.3 UART Setup for GUI Communication
            4. 2.3.2.3.1.4 Real-Time Clock (RTC)
            5. 2.3.2.3.1.5 LCD Controller
            6. 2.3.2.3.1.6 Direct Memory Access (DMA)
            7. 2.3.2.3.1.7 ADC Setup
          2. 2.3.2.3.2 Foreground Process
            1. 2.3.2.3.2.1 Formulas
          3. 2.3.2.3.3 Background Process
            1. 2.3.2.3.3.1 per_sample_dsp()
              1. 2.3.2.3.3.1.1 Voltage and Current Signals
              2. 2.3.2.3.3.1.2 Frequency Measurement and Cycle Tracking
            2. 2.3.2.3.3.2 LED Pulse Generation
            3. 2.3.2.3.3.3 Phase Compensation
    4. 2.4 Hardware, Software, Testing Requirements, and Test Results
      1. 2.4.1 Required Hardware and Software
        1. 2.4.1.1 Cautions and Warnings
        2. 2.4.1.2 Hardware
          1. 2.4.1.2.1 Connections to the Test Setup
          2. 2.4.1.2.2 Power Supply Options and Jumper Settings
        3. 2.4.1.3 Software
      2. 2.4.2 Testing and Results
        1. 2.4.2.1 Test Setup
          1. 2.4.2.1.1 SVS and Cap-Drop Functionality Testing
          2. 2.4.2.1.2 Electricity Meter Metrology Accuracy Testing
          3. 2.4.2.1.3 Current-Detection Mode Testing
          4. 2.4.2.1.4 Viewing Metrology Readings and Calibration
            1. 2.4.2.1.4.1 Viewing Results From LCD
            2. 2.4.2.1.4.2 Calibrating and Viewing Results From PC
              1. 2.4.2.1.4.2.1 Viewing Results
              2. 2.4.2.1.4.2.2 Calibration
                1. 2.4.2.1.4.2.2.1 Gain Calibration
                  1. 4.2.1.4.2.2.1.1 Voltage and Current Gain Calibration
                  2. 4.2.1.4.2.2.1.2 Active Power Gain Calibration
                2. 2.4.2.1.4.2.2.2 Offset Calibration
                3. 2.4.2.1.4.2.2.3 Phase Calibration
        2. 2.4.2.2 Test Results
          1. 2.4.2.2.1 SVS and TPS7A78 Functionality Testing Results
          2. 2.4.2.2.2 Electricity Meter Metrology Accuracy Results
          3. 2.4.2.2.3 Current-Detection Mode Results
  8. 3Design Files
    1. 3.1 Schematics
    2. 3.2 Bill of Materials
    3. 3.3 PCB Layout Recommendations
      1. 3.3.1 Layout Prints
    4. 3.4 Altium Project
    5. 3.5 Gerber Files
    6. 3.6 Assembly Drawings
  9. 4Related Documentation
    1. 4.1 Trademarks
  10. 5About the Author
  11. 6Revision History
2.3.1.3.2 Current Measurement Analog Front End

The analog front end for current inputs is different from the analog front end for the voltage inputs. Figure 2-5 shows the analog front end used for the CT current channel, where the positive and negative leads from a CT are connected to pins 3 and 1 of header J26.

GUID-0E0C585C-4C19-4DBE-8952-5E2911A4F5D9-low.gifFigure 2-5 Analog Front End for CT Current Inputs

The analog front end for current consists of footprints for electromagnetic interference filter beads (R48 and R57), burden resistors for current transformers (R51 and R56), and an RC low-pass filter (R49, R58, C52, C53, and C54) that functions as an anti-alias filter. There are also footprints (U12 and U13) that can be replaced with the TVS0500 for supplemental protection from surges, if required.

As Figure 2-5 shows, resistors R51 and R56 are the burden resistors, which are in series with each other. For best THD performance, instead of using one burden resistor, two identical burden resistors in series are used with the common point being connected to GND. This split-burden resistor configuration ensures that the waveforms fed to the positive and negative terminals of the ADC are 180 degrees out of phase with each other, which provides the best THD results with this ADC. The total burden resistance is selected based on the current range used and the turns ratio specification of the CT (this design uses CTs with a turns ratio of 2000). The total value of the burden resistor for this design is 12.98 Ω.

Equation 2 shows how to calculate the range of differential voltages fed to the current ADC channel for a given maximum current, CT turns ratio, and burden resistor value.

Equation 2. GUID-397F7C38-DCB4-4503-A837-9B1898956514-low.gif

Based on the maximum current of 100 A, CT turns ratio of 2000, and burden resistor of 12.98 Ω of this design, the input signal to the current ADC has a voltage swing of ±918 mV maximum (649 mVRMS) when the maximum current rating of the meter (100 A) is applied. This ±918-mV maximum input voltage is well within the ±1.2-V input range of the device for the selected PGA gain of 1 that is used for the current channels.

Figure 2-6 shows the analog front end used for the shunt current channel, where the positive and negative leads from the shunt are connected to pins 1 and 3 of header J25. The ground connection for the shunt is connected to pin 2 of this J25 header.

GUID-4E3B9E3D-1DAD-43B9-8F3F-6584E8E6E394-low.gifFigure 2-6 Analog Front End for Shunt Current Inputs

The circuitry in Figure 2-6 is similar to the circuit shown for the CT channel, except the R51 and R56 burden resistors are now removed since a shunt is used instead of a CT. Since the burden resistors have been removed, do not connect a CT to this channel because it may cause a large output voltage that may damage the meter. In addition, note that the pin order of the AINxP and AINxN pins on the ADS131M04 device is swapped when going from one converter to another. As an example, AIN1N is pin 5 and AIN1P is pin 6, but AIN2P is pin 7 and AIN2N is pin 8. The swapped order is why the order of the CT positive output terminal and negative output terminal on J26 is swapped when compared to the shunt positive and negative output terminal on J25.

Equation 2 shows how to calculate the range of differential voltages fed to the current ADC channel for a given maximum current and shunt value.

Equation 3. GUID-7C38A7E9-DA0B-44BA-B2A3-C14EC04F7DEF-low.gif

With shunt current sensors, the shunt sensor value is selected based on the tradeoff between accuracy and shunt power dissipation. If the shunt value is decreased, less power is dissipated through the shunt; however, the decreased shunt value means a smaller output voltage from the shunt, which leads to worse accuracies at lower currents, even if a higher PGA gain is used to boost the shunt output. In this design, tests are performed with both 100- and 200-µΩ shunts.

Based on the VADC,shunt range, select the proper PGA gain by looking at the full-scale range table in Table 2-1 to find the two gain ranges that VADC,shunt, shunt voltage fits between. From these two gain values, select the lower gain setting as the selected PGA gain value for the shunt channel. This gain value maximizes the ADC range without saturation occurring at higher currents. As an example of this process, suppose a 100-A maximum RMS current and a 200-µΩ shunt is used. Based on these values, VADC,shunt varies between ±28.3 mV. This voltage range is between the maximum ±37.5 mV voltage at a gain of 32 and ±18.75 mV at a PGA gain of 64 so the PGA gain setting of the shunt channel is set for 32.

Table 2-1 Full-Scale Range
GAIN SETTINGFSR
1±1.2 V
2±600 mV
4±300 mV
8±150 mV
16±75 mV
32±37.5 mV
64±18.75 mV
128±9.375 mV