TIDUEM7A April 2019 – February 2021
To have the ADS131M04 device enter current-detection mode regularly without CPU intervention, one option is to connect the timer output of an MCU to the SYNC/ RST pin on the ADS131M04 device. The timer can be set to have its output provide the necessary pulse to cause the ADS131M04 device to enter current-detection mode from standby mode at regular intervals. In this design, the pin connected to the ADS131M04 SYNC/ RESET pin can be port mapped to a timer output from one of the timer A modules of the MSP432 MCU. This timer can be clocked from the low-frequency crystal on the board, which enables the timer to be functional if the MSP432 MCU were to enter a low-power mode where SMCLK and its CPU clock were disabled, thereby enabling the reduction of the system current consumption.
In this design, the timer for driving the SYNC/ Reset pin is configured to count in up-mode, where the timer counts to a value set in its TAxCCR0 register. After counting up to TAxCCR0, the timer is reset back to 0 at the next timer clock cycle. Figure 2-9 shows the timer output connected to the SYNC/ Reset pin is set for a “reset/set” output mode. In this mode, the SYNC/ Reset pin is asserted low when the timer first counts up to the value in the TAxCCR1 register and the pin is asserted high when the timer counts back to 0 again. To enter current-detection mode immediately, the timer count is initialized with a value equal to TAxCCR1 before the timer is first started.
The TAxCCR0 register and the frequency of the timer sets the frequency for entering into current-detection mode. The timer A module of the MSP432 MCU has clock dividers, which are used to divide the clock source for a slower frequency timer. Equation 4 shows the frequency of the timer based on the selected clock divider.
The time between triggers to enter current-detection mode can be calculated with Equation 5:
The duration of the time of when the SYNC/ RESET pin is held low, the negative pulse width time, is also calculated as Equation 6 shows:
As an example, suppose that the frequency of the timer clock source is 32,768 Hz and the values of TAxCCR0 and TAXCCR1 registers are 65,535, which is the maximum value that these two 16-bit registers could hold. If current-detection mode is desired to occur once every 10 seconds, then the timer clock divider can be set to a value to 5, which results in a timer frequency of 6553.6 Hz and a negative pulse width time of 153 microseconds. As a different example, if current-detection mode is to occur once very 64 seconds, then the timer clock divider value can be set to 32, which results in a timer frequency of 1024 Hz and a negative pulse width time of 977 microseconds.