TIDUEM8B March   2019  – February 2021

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
  6.   6
    1.     7
      1.      8
      2.      9
    2.     10
  7.   11
    1.     12
    2.     13
      1.      14
      2.      15
      3.      16
      4.      17
      5.      18
      6.      19
      7.      20
      8.      21
      9.      22
      10.      23
    3.     24
      1.      25
        1.       26
        2.       27
        3.       28
        4.       29
          1.        30
          2.        31
      2.      32
        1.       33
          1.        34
          2.        35
          3.        36
          4.        37
          5.        38
          6.        39
          7.        40
        2.       41
          1.        42
        3.       43
          1.        44
            1.         45
            2.         46
          2.        47
          3.        48
  8.   49
    1.     50
      1.      51
      2.      52
        1.       53
          1.        54
          2.        55
        2.       56
      3.      57
    2.     58
      1.      59
        1.       60
        2.       61
        3.       62
          1.        63
          2.        64
            1.         65
            2.         66
              1.          67
                1.           68
                2.           69
              2.          70
              3.          71
      2.      72
        1.       73
        2.       74
  9.   75
    1.     76
    2.     77
    3.     78
      1.      79
    4.     80
    5.     81
    6.     82
  10.   83
    1.     84
  11.   85
  12.   86
2.3.1.4.1 Voltage Measurement Analog Front End

The nominal voltage from the mains is from 100 V–240 V so it needs to be scaled down to be sensed by an ADC. Figure 2-5 shows the analog front end used for this voltage scaling. J28 is where the voltage is applied.

GUID-FCA5F6AF-1FAF-4CF6-99F2-F417B278F0DB-low.gifFigure 2-5 Analog Front End for Voltage Inputs

In the analog front end for voltage, there consists a spike protection varistor (R87), footprints for electromagnetic interference filter beads (resistor footprints R103 and R104) , a voltage divider network (R105, R106, R107, and R108), and an RC low-pass filter (R109, R110, C103, C104, and C105).

At lower currents, voltage-to-current crosstalk affects active energy accuracy much more than voltage accuracy, if power offset calibration is not performed. To maximize the accuracy at these lower currents, in this design the entire ADC range is not used for voltage channels. Since the ADCs of the ADS131M04 device are high-accuracy ADCs, using the reduced ADC range for the voltage channels in this design still provides more than enough accuracy for measuring voltage. Equation 1 shows how to calculate the range of differential voltages fed to the voltage ADC channel for a given Mains voltage and selected voltage divider resistor values.

Equation 1. GUID-5480165F-A7BF-4874-AB16-1FF99E1ECD2E-low.gif

Based on this formula and the selected resistor values in Figure 2-5, for a mains voltage of 120 V (as measured between the line and neutral), the input signal to the voltage ADC has a voltage swing of ±128 mV (91 mVRMS) when using the two-voltage configuration. For the one-voltage configuration, for a mains voltage of 120 V (as measured between the line and neutral), 240 V would be input to the front-end circuit in Figure 2-5 since the line-to-line voltage is measured instead of the line-to-neutral voltage. The 240-V input to the front-end circuit produces a voltage swing of ±257 mV (182 mVRMS). The ±128-mV and the ±257-mV voltage ranges for the two-voltage and one-voltage configurations are both well within the ±1.2-V input voltage that can be sensed by the ADS131M04 device for the selected PGA gain value of 1 that is used for the voltage channels.

Note that the pin order of the AINxP and AINxN pins on the ADS131M04 is swapped when going from one converter to another. As an example, AIN2P is pin 7 and AIN2N is pin 8 but AIN3N is pin 9 and AIN3P is pin 10. The swapped order is why the order of the positive input voltage and negative input voltage is swapped between the J28 voltage input terminal block of Phase A and the J29 voltage input terminal block of Phase B.