TIDUEP0 May 2020
Figure 20 shows the schematic of the data and power connector placed on the board. 2 set of connectors are placed on the board to connect to the TX+RX AFE Board. Multiple signals are also coming from the FPGA to communicate with the FX3 device. A clock signal named DC_DC_CLK 1 of 1MHz frequency is coming from the FPGA to be the source clock for the power supply clock synchronization. 32 bit data line are also coming from the FPGA to the data serializer device FX3. Different Power rails are distributed among the connectors for ease of layout and keeping the routing length short. The High voltage rails are put separately on two connector ensuring equal lengths and separation. They are routed along the edge of the board too to keep it away from sensitive circuitry. The connector used is Panasonic’s AXK5S80347YG.