TIDUES6 August   2020  – MONTH 

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 DRV8906-Q1
      2. 2.3.2 DRV8873-Q1
      3. 2.3.3 TPS1HB16-Q1
      4. 2.3.4 LM2904B-Q1
      5. 2.3.5 TLIN1028-Q1
    4. 2.4 System Design Theory
      1. 2.4.1 Mirror XY and LED Driver
      2. 2.4.2 Mirror Fold Driver
      3. 2.4.3 Mirror Heater Driver for Defogging and De-icing
      4. 2.4.4 Electrochromic Mirror Driver
        1. 2.4.4.1 Sallen-Key Low-Pass Filter
        2. 2.4.4.2 High-Current Buffer Amplifier
        3. 2.4.4.3 Buffer Amplifier Stability for Very-Large Capacitive Loads
        4. 2.4.4.4 Fast Discharge of Large Capacitive Load
      5. 2.4.5 SBC - LIN Communication Interface and System Supply
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
    2. 3.2 Testing and Results
      1. 3.2.1 Test Setup
      2. 3.2.2 Test Results
        1. 3.2.2.1 Reverse Battery Protection
        2. 3.2.2.2 X&Y Motors and LED Driver
        3. 3.2.2.3 Thermal Performance
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 Altium Project
    4. 4.4 Gerber Files
    5. 4.5 Assembly Drawings
  10. 5Software Files
  11. 6Related Documentation
    1. 6.1 Trademarks
    2. 6.2 Third-Party Products Disclaimer
  12. 7Terminology

Buffer Amplifier Stability for Very-Large Capacitive Loads

Due to the size of the capacitive load, stability of the buffer amplifier is a concern. Designers can improve capacitive load stability through the use of both noise gain and capacitive feedback compensation. Using rate of closure analysis provides a guideline on the expected phase margin on an amplifier based on the angle of the slopes between the modified open loop gain and 1/β bode plots. A key rule is to ensure the rate of closure is not greater than 20 dB/decade, which ensures the phase margin of the design is greater than 45°. For more information on op amps and stability, see the training resource TI Precision Labs - Ops Amps: Stability 2.

The noise gain compensation consists of implementing high-frequency gain to allow the 1/β of the amplifier to be larger than the modified open-loop gain at the pole introduced by the capacitive load, which allows the rate of the closure to be 20 dB/decade rather than 40 dB/decade. This method retains the desired 0-dB gain at DC that allows the amplifier to continue to operate as a buffer. The noise gain provides the necessary bump in the phase margin to maintain stability across the entire bandwidth of the amplifier and prevent ringing.

This high-frequency gain is implemented with R1, R3, and C6, which creates a zero and provides a 20-dB/decade slope on the 1/β plot above approximately 1 kHz. The rate of closure at the intersection is then |–40 dB/decade + 20 dB/decade| = 20 dB/decade.

To add to the stability improvements found with noise gain, an additional capacitor C1 is used to implement a capacitive feedback, or Cf, compensation. This additional high-frequency pole boosts the phase even more in the area of concern.

Figure 2-11 shows a TINA simulation of the bode plot without the noise gain implemented and Figure 2-12 shows the result of the noise gain.

GUID-C0990A5E-511F-4E41-AEE3-73C92E5A321D-low.pngFigure 2-11 TINA-TI™ Stability Analysis of EC Mirror Driver Without Compensation
GUID-94111804-550A-462F-8689-1187752BEC2B-low.pngFigure 2-12 TINA-TI™ Stability Analysis of EC Mirror Driver With Compensation