TIDUEX0A November 2020 – December 2020
The reference design is based on the DRA821 SoC which is heterogeneous automotive processor with dual ARM Cortex-A72 cores and four ARM R5Fs to support a variety of processing and real-time applications. The DRA821 also has an integrated 4-port Ethernet switch, 20 CAN-FD interfaces, PCIe, an integrated HSM, and up to ASIL-D systematic capability to ensure safe and secure data communication of high bandwidth data in gateway applications.
The reference design is based off of a single TPS6594x PMIC. The power topology is based off a 12V input to the PMIC in conjunction with several discrete bucks. The TPS6594x-Q1 is a PMIC that integrates optimized power management, ASIL-D features, and wakeup functionality into a chip.
[Integrated Switch]
Two 1000Base automotive connectors are connected to the DRA821 integrated 4-port gigabit Ethernet switch ports via SGMII. The integrated switch supports a diverse set of interfaces including one 2.5 GB XFI or SGMII, up to four 1 Gb SGMII, up to four RMII (10/100) or RGMII (10/100/1000), and one 5GB QSGMII. Time synchronization functions to support IEEE 1588 (annex D,E,F) are also integrated for TSN/AVB support.
[External Switch]
The RealTek RTL9068 switch is connected to the DRA821 integrated gigabyte Ethernet switch through USXGMII (up to 5Gbps). An RJ45 100Base connector, and two 1000Base automotive connectors are sourced from the RTL9068.
There are five TCAN1046 devices on the board to support a total of 10 CAN connections. The TCAN1046 is a dual-CAN transceiver that supports both classical CAN and CAN-FD bus networks up to 8 Mbps.
There are two TLIN1022 devices on the board to support a total of four LIN connections. The TLIN1022-Q1 is a Dual Local Interconnect Network (LIN) physical layer transceiver with integrated wake-up and protection features (up to 12V), complaint up to LIN 2.2A standards.
Wakeup functionality can be achieved via any of the CAN, LIN, of GPIO inputs – which are on their own I/O standby domain enabling power savings and wakeup synergy.
The reference design uses a single MT53D512M32D2DS Micron memory banks for a total of 2 GB of onboard LPDDR4 memory running at 2666 MT/s. Micron’s MTFC8GAMALNA provides 8 GB of on-board NAND flash, connected to DRA821’s eMMC interface. To support fast booting over OSPI, the board uses Cypress’s S28HS512T for 64 MB of NOR Flash.
The board contains several extra headers enabling access to GPIO, SPI, I2C, ADC and ECAP. There are also dedicated CAN transceivers, LIN transceivers, and automotive Ethernet connectors on board. A standard PCIe connector supports high bandwidth communication. Due to pin muxing limitations, if SGMII and QSGMII are used the PCIe connector will operate via 1–Lane at Gen 2 speeds. If the SGMII or QSGMII ports are not used, then 2-Lane at Gen 3 speed entitlement can be obtained. More information can be obtained by looking at SERDES pin muxing documentation. Refer to 4-L Serializer/Deserializer (SERDES) section of the technical reference manual
JTAG, SD Card, and USB-UART over mini USB A/B connectors are available for debug ports.