TIDUEY8 March   2023

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Design Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 LMK04832-SP
      2. 2.2.2 LMX2615-SP
      3. 2.2.3 CDCLVP111-SP
      4. 2.2.4 ADC12DJ3200QML-SP
    3. 2.3 Design Steps
      1. 2.3.1 Multiple JESD204B Synchronization Requirements
      2. 2.3.2 Clock Tree Design
        1. 2.3.2.1 Clock Frequency Plan
        2. 2.3.2.2 Clock Tree Components
          1. 2.3.2.2.1 Clock Reference
          2. 2.3.2.2.2 Clock Reference Buffer
          3. 2.3.2.2.3 Clock Distribution
          4. 2.3.2.2.4 Frequency Synthesis
        3. 2.3.2.3 Phase Delay Adjustment Options
        4. 2.3.2.4 Phase-Noise Optimization
        5. 2.3.2.5 Single-Event Effects (SEE) Considerations
        6. 2.3.2.6 Expanding Clock Tree for MIMO Systems
      3. 2.3.3 Power Management
        1. 2.3.3.1 Power Design Considerations
        2. 2.3.3.2 Radiation Hardened (Rad-Hard) Power Tree
          1. 2.3.3.2.1 Radiation-Hardness-Assured (RHA) Load-Switches
          2. 2.3.3.2.2 Radiation-Hardness-Assured (RHA) DC/DC Buck Converter
          3. 2.3.3.2.3 Radiation-Hardness-Assured (RHA) Low-Dropout (LDO) Regulators
            1. 2.3.3.2.3.1 3.3-V Linear Regulator
            2. 2.3.3.2.3.2 4.5-V Linear Regulator
        3. 2.3.3.3 Overcurrent Detection Circuit
  8. 3Getting Started Hardware and Software
    1. 3.1 Hardware Configuration
      1. 3.1.1 Clocking Board Setup
        1. 3.1.1.1 Power Supply
        2. 3.1.1.2 Input Reference Signals
        3. 3.1.1.3 Input sync Signal
        4. 3.1.1.4 Output Signals
        5. 3.1.1.5 Programming Interface
        6. 3.1.1.6 FMC+ Adapter Board Setup
        7. 3.1.1.7 ADC12DJ3200 EVM Setup
        8. 3.1.1.8 TSW14J57EVM Setup
        9. 3.1.1.9 Multichannel Synchronization Setup
    2. 3.2 Software
      1. 3.2.1 Software Required
      2. 3.2.2 Clocking Board Programming Sequence
      3. 3.2.3 ADC12DJ3200CVAL EVM Programming Sequence
      4. 3.2.4 TSW14J57EVM Evaluation Programming Sequence
  9. 4Testing and Results
    1. 4.1 Test Setup
    2. 4.2 Results
      1. 4.2.1 Phase Noise Measurement Results
      2. 4.2.2 Multichannel Clock Phase Alignment
      3. 4.2.3 Signal Chain Performance
      4. 4.2.4 Channel-to-Channel Skew Measurement
    3. 4.3 Summary and Conclusion
  10. 5Design and Documentation Support
    1. 5.1 Design Support
      1. 5.1.1 Schematics
      2. 5.1.2 Bill of Materials
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4. 5.4 Trademarks
  11. 6About the Authors
    1. 6.1 Acknowledgments

2.3.3.2 Radiation Hardened (Rad-Hard) Power Tree

Clocking devices used in this reference design primarily require a 3.3-V supply voltage. Providing a low noise 3.3-V supply is a main focus for the power tree (see Figure 2-12). Furthermore, the power supply needs to meet radiation requirements typical for multi-year missions in GEO orbits. In this specific case all of the power tree integrated circuits (ICs) are rad-hard and meet or exceed the following radiation specifications:

  • Total Ionizing Dose (TID) Characterization = 100 krad (Si)
  • Radiation-Hardness-Assured (RHA) / RLAT = 100 krad (Si)
  • Neutron Displacement Damage (NDD) Characterization = 1 × 1013 n/cm2 (1 MeV equivalent)
  • SEL, SEB, and SEGR Immune to LET = 75 MeV/cm2/mg
  • SET, SEFI Characterized to LET = 75 MeV/cm2/mg
Note: Because this reference design focuses on selecting appropriate semiconductor devices, discrete components (for example, resistors, capacitors, diodes, inductors, and so forth) are used irrespective of space-qualification.
GUID-20221202-SS0I-FF4G-MTBJ-GGK3MNCH1H1R-low.svgFigure 2-12 Power Tree

Figure 2-12 shows the power tree. From left to right, the power tree demonstrates three types of rad-hard power devices. First the TPS7H2201-SP eFuse provides an integrated option to provide overcurrent and overvoltage protection functions. Next, the TPS50601A-SP DC/DC buck converter does the efficient conversion from 5.0 V down to 3.8 V. This leaves 500-mV headroom for the 3.3-V LDOs so that LDO can perform with excellent AC performance. The TPS7H1101A-SP then does the conversion from 3.8 V down to 3.3 V. The LDO responsible for the 4.5-V supply of the differential amplifiers, the TPS7A4501, runs directly off the 5-V supply because at that low current the use of a switch mode converter is not needed.