TIDUEY8 March   2023

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Design Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 LMK04832-SP
      2. 2.2.2 LMX2615-SP
      3. 2.2.3 CDCLVP111-SP
      4. 2.2.4 ADC12DJ3200QML-SP
    3. 2.3 Design Steps
      1. 2.3.1 Multiple JESD204B Synchronization Requirements
      2. 2.3.2 Clock Tree Design
        1. 2.3.2.1 Clock Frequency Plan
        2. 2.3.2.2 Clock Tree Components
          1. 2.3.2.2.1 Clock Reference
          2. 2.3.2.2.2 Clock Reference Buffer
          3. 2.3.2.2.3 Clock Distribution
          4. 2.3.2.2.4 Frequency Synthesis
        3. 2.3.2.3 Phase Delay Adjustment Options
        4. 2.3.2.4 Phase-Noise Optimization
        5. 2.3.2.5 Single-Event Effects (SEE) Considerations
        6. 2.3.2.6 Expanding Clock Tree for MIMO Systems
      3. 2.3.3 Power Management
        1. 2.3.3.1 Power Design Considerations
        2. 2.3.3.2 Radiation Hardened (Rad-Hard) Power Tree
          1. 2.3.3.2.1 Radiation-Hardness-Assured (RHA) Load-Switches
          2. 2.3.3.2.2 Radiation-Hardness-Assured (RHA) DC/DC Buck Converter
          3. 2.3.3.2.3 Radiation-Hardness-Assured (RHA) Low-Dropout (LDO) Regulators
            1. 2.3.3.2.3.1 3.3-V Linear Regulator
            2. 2.3.3.2.3.2 4.5-V Linear Regulator
        3. 2.3.3.3 Overcurrent Detection Circuit
  8. 3Getting Started Hardware and Software
    1. 3.1 Hardware Configuration
      1. 3.1.1 Clocking Board Setup
        1. 3.1.1.1 Power Supply
        2. 3.1.1.2 Input Reference Signals
        3. 3.1.1.3 Input sync Signal
        4. 3.1.1.4 Output Signals
        5. 3.1.1.5 Programming Interface
        6. 3.1.1.6 FMC+ Adapter Board Setup
        7. 3.1.1.7 ADC12DJ3200 EVM Setup
        8. 3.1.1.8 TSW14J57EVM Setup
        9. 3.1.1.9 Multichannel Synchronization Setup
    2. 3.2 Software
      1. 3.2.1 Software Required
      2. 3.2.2 Clocking Board Programming Sequence
      3. 3.2.3 ADC12DJ3200CVAL EVM Programming Sequence
      4. 3.2.4 TSW14J57EVM Evaluation Programming Sequence
  9. 4Testing and Results
    1. 4.1 Test Setup
    2. 4.2 Results
      1. 4.2.1 Phase Noise Measurement Results
      2. 4.2.2 Multichannel Clock Phase Alignment
      3. 4.2.3 Signal Chain Performance
      4. 4.2.4 Channel-to-Channel Skew Measurement
    3. 4.3 Summary and Conclusion
  10. 5Design and Documentation Support
    1. 5.1 Design Support
      1. 5.1.1 Schematics
      2. 5.1.2 Bill of Materials
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4. 5.4 Trademarks
  11. 6About the Authors
    1. 6.1 Acknowledgments

2.3.2.1 Clock Frequency Plan

A JESD204B-compliant clock output from the board is given to ADC12DJ3200QML-SP. Because SNR of the ADC is directly affected by clock jitter, the ADC is used to analyze the performance of the clocking board. The ADC12DJ3200QML-SP can go up to a 3.2-GHz clock frequency. The LMK04832-SP is configured in single PLL mode (PLL2) to generate SYSREF_REQ and SYNC signals to LMX2615-SP devices. The LMK04832-SP on this reference design is also used to provide an FPGA reference clock, a core clock, and SYSREF to the TSW14J57 capture card through the FMC+ adapter board. The clock reference and core clock frequency are both 160 MHz and the SYSREF frequency is 20 MHz. The adapter board also provides the interface between the data converter EVM and the capture card while also connecting the ADC data lanes to the FPGA.

ADC12DJ3200EVMCVAL operates in dual-channel mode (JMODE3) where input to only one channel is provided and output from the corresponding ADC core is captured. An input reference frequency of 100 MHz is provided to the LMX2615-SP RF PLL clock synthesizer device by LMK61E2 via CDCLVP111-SP. The phase-detector frequency is also changed to 100 MHz. Various input signals are available at the ADC input for SNR measurement and results are shown in Section 4, Testing and Results.

Table 2-1 Loop-Filter Configuration
CLOCK REFERENCELMK04832-SP CLOCK PLL2 MODELMX2615-SP PLL SYNTHESIZERADC CLOCKINGFPGA CLOCKING
Clock Reference SelectedList Clock Inputs/OutputsClock Inputs and Clock OutputsClocks Inputs/Outputs Clocks Inputs/Outputs
Other Options:
  1. VCXO
  2. Programmable Oscillator (LMK6E12) – 100 MHz
  3. External reference
Input REF (OSCin) – 100 MHz

Output clocks:

CLKout1 – LMX2615-1 SYSREF_REQ1 (20 MHz)

CLKout3 – LMX2615-2 SYSREF_REQ2 (20 MHz)

CLKout4 – FPGA2 REFCLK

CLKout5 – LMX2615-1 SYNC1

CLKout6 – FPGA2 CORECLK

CLKout7 – FPGA2 SYSREF

CLKout8 – FPGA1 CORECLK

CLKout9 – FPGA1 SYSREF

CLKout10 – FPGA1 REFCLK

CLKout11 – LMX2615-2 SYNC2

LMX2615-1:

Input REF (OSCin) – 100 MHz

SYNC - SYNC1

SYSREFREQ - SYSREF_REQ1

Output clocks:

RFoutA1 – ADC1 CLK

RFoutB1– ADC1 SYSREF

LMX2615-2:

Input REF (OSCin) – 100 MHz

SYNC – SYNC2

SYSREFREQ – SYSREF_REQ2

Output clocks:

RFoutA2 – ADC2 CLK

RFoutB2 – ADC2 SYSREF

Sampling Clock: 3.2-GHz

SYSREF – 20 MHz

FPGA REFCLK – 160 MHz

FPGA CORECLK – 160 MHz

FPGA SYSREF – 20 MHz