TIDUEY8 March   2023

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Design Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 LMK04832-SP
      2. 2.2.2 LMX2615-SP
      3. 2.2.3 CDCLVP111-SP
      4. 2.2.4 ADC12DJ3200QML-SP
    3. 2.3 Design Steps
      1. 2.3.1 Multiple JESD204B Synchronization Requirements
      2. 2.3.2 Clock Tree Design
        1. 2.3.2.1 Clock Frequency Plan
        2. 2.3.2.2 Clock Tree Components
          1. 2.3.2.2.1 Clock Reference
          2. 2.3.2.2.2 Clock Reference Buffer
          3. 2.3.2.2.3 Clock Distribution
          4. 2.3.2.2.4 Frequency Synthesis
        3. 2.3.2.3 Phase Delay Adjustment Options
        4. 2.3.2.4 Phase-Noise Optimization
        5. 2.3.2.5 Single-Event Effects (SEE) Considerations
        6. 2.3.2.6 Expanding Clock Tree for MIMO Systems
      3. 2.3.3 Power Management
        1. 2.3.3.1 Power Design Considerations
        2. 2.3.3.2 Radiation Hardened (Rad-Hard) Power Tree
          1. 2.3.3.2.1 Radiation-Hardness-Assured (RHA) Load-Switches
          2. 2.3.3.2.2 Radiation-Hardness-Assured (RHA) DC/DC Buck Converter
          3. 2.3.3.2.3 Radiation-Hardness-Assured (RHA) Low-Dropout (LDO) Regulators
            1. 2.3.3.2.3.1 3.3-V Linear Regulator
            2. 2.3.3.2.3.2 4.5-V Linear Regulator
        3. 2.3.3.3 Overcurrent Detection Circuit
  8. 3Getting Started Hardware and Software
    1. 3.1 Hardware Configuration
      1. 3.1.1 Clocking Board Setup
        1. 3.1.1.1 Power Supply
        2. 3.1.1.2 Input Reference Signals
        3. 3.1.1.3 Input sync Signal
        4. 3.1.1.4 Output Signals
        5. 3.1.1.5 Programming Interface
        6. 3.1.1.6 FMC+ Adapter Board Setup
        7. 3.1.1.7 ADC12DJ3200 EVM Setup
        8. 3.1.1.8 TSW14J57EVM Setup
        9. 3.1.1.9 Multichannel Synchronization Setup
    2. 3.2 Software
      1. 3.2.1 Software Required
      2. 3.2.2 Clocking Board Programming Sequence
      3. 3.2.3 ADC12DJ3200CVAL EVM Programming Sequence
      4. 3.2.4 TSW14J57EVM Evaluation Programming Sequence
  9. 4Testing and Results
    1. 4.1 Test Setup
    2. 4.2 Results
      1. 4.2.1 Phase Noise Measurement Results
      2. 4.2.2 Multichannel Clock Phase Alignment
      3. 4.2.3 Signal Chain Performance
      4. 4.2.4 Channel-to-Channel Skew Measurement
    3. 4.3 Summary and Conclusion
  10. 5Design and Documentation Support
    1. 5.1 Design Support
      1. 5.1.1 Schematics
      2. 5.1.2 Bill of Materials
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4. 5.4 Trademarks
  11. 6About the Authors
    1. 6.1 Acknowledgments

2.3.2.5 Single-Event Effects (SEE) Considerations

In this reference design the ADC12DJ3200QML-SP RF Sampling ADC is the target data converter for which to provide a clock tree. For more information about the single event upset (SEU) and how to handle SEUs, see the ADCDJ3200QML-SP data sheet: ADC12DJ3200QML-SP 6.4-GSPS, Single-Channel or 3.2-GSPS, Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC).

JESD204B outlines that SYSREF can be configured in different modes, continuous (also known as periodic), gapped periodic, or one-shot signal. Continuous mode allows for continuous output which designers sometimes need to avoid due to crosstalk from SYSREF to the device clock. However, the ADC12DJ3200QML-SP data sheet recommends always using a continuous SYSREF to quickly recover internal clocks and counters that can experience SEUs.

To minimize concerns of crosstalk from SYSREF to the device clock, set the period to be long enough to limit spurious performance degradation caused by coupling, but short enough to recover within the system requirements. SYSREF helps both the transmitter (ADC12DJ3200QML-SP) and receiver (FPGA or ASIC) recover after an SEU. See the single event upset (SEU) section of the ADC12DJ3200QML-SP data sheet for additional recommendations.

In the design, the core in the clock tree (LMK04832-SP, LMX2615-SP), as well as the target data converter (ADC12DJ3200QML-SP) are free of Single-Event Functional Interrupts (SEFI) to a LET ≥ 80 MeV⋅cm2/mg. Table 2-3 provides an overview for a summary for the radiation performance of these devices.

Table 2-3 Summary for the Radiation Performance
PARAMETERADC12DJ3200QML-SPLMK04832-SPLMX2615-SPCDCLVP111-SP
TID LDR Characterization [krad(Si)]

N/A

100

100

75

TID HDR Characterization [krad(Si)]

300

100

100

100

TID RLAT/RHA [krad(Si)]

300

100

100

—

SEL Immunity [MeV⋅cm2/mg]

120

120

120

69.2

SEFI Immunity [MeV⋅cm2/mg]

120

120

120 (Pin Mode)

—

SEE Characterization [MeV⋅cm2/mg]12012012065.3

For additional device-specific information refer to the Single-Event Effects (SEE) reports, typically available in the TI.com product folders.