TIDUEY8 March   2023

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Design Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 LMK04832-SP
      2. 2.2.2 LMX2615-SP
      3. 2.2.3 CDCLVP111-SP
      4. 2.2.4 ADC12DJ3200QML-SP
    3. 2.3 Design Steps
      1. 2.3.1 Multiple JESD204B Synchronization Requirements
      2. 2.3.2 Clock Tree Design
        1. 2.3.2.1 Clock Frequency Plan
        2. 2.3.2.2 Clock Tree Components
          1. 2.3.2.2.1 Clock Reference
          2. 2.3.2.2.2 Clock Reference Buffer
          3. 2.3.2.2.3 Clock Distribution
          4. 2.3.2.2.4 Frequency Synthesis
        3. 2.3.2.3 Phase Delay Adjustment Options
        4. 2.3.2.4 Phase-Noise Optimization
        5. 2.3.2.5 Single-Event Effects (SEE) Considerations
        6. 2.3.2.6 Expanding Clock Tree for MIMO Systems
      3. 2.3.3 Power Management
        1. 2.3.3.1 Power Design Considerations
        2. 2.3.3.2 Radiation Hardened (Rad-Hard) Power Tree
          1. 2.3.3.2.1 Radiation-Hardness-Assured (RHA) Load-Switches
          2. 2.3.3.2.2 Radiation-Hardness-Assured (RHA) DC/DC Buck Converter
          3. 2.3.3.2.3 Radiation-Hardness-Assured (RHA) Low-Dropout (LDO) Regulators
            1. 2.3.3.2.3.1 3.3-V Linear Regulator
            2. 2.3.3.2.3.2 4.5-V Linear Regulator
        3. 2.3.3.3 Overcurrent Detection Circuit
  8. 3Getting Started Hardware and Software
    1. 3.1 Hardware Configuration
      1. 3.1.1 Clocking Board Setup
        1. 3.1.1.1 Power Supply
        2. 3.1.1.2 Input Reference Signals
        3. 3.1.1.3 Input sync Signal
        4. 3.1.1.4 Output Signals
        5. 3.1.1.5 Programming Interface
        6. 3.1.1.6 FMC+ Adapter Board Setup
        7. 3.1.1.7 ADC12DJ3200 EVM Setup
        8. 3.1.1.8 TSW14J57EVM Setup
        9. 3.1.1.9 Multichannel Synchronization Setup
    2. 3.2 Software
      1. 3.2.1 Software Required
      2. 3.2.2 Clocking Board Programming Sequence
      3. 3.2.3 ADC12DJ3200CVAL EVM Programming Sequence
      4. 3.2.4 TSW14J57EVM Evaluation Programming Sequence
  9. 4Testing and Results
    1. 4.1 Test Setup
    2. 4.2 Results
      1. 4.2.1 Phase Noise Measurement Results
      2. 4.2.2 Multichannel Clock Phase Alignment
      3. 4.2.3 Signal Chain Performance
      4. 4.2.4 Channel-to-Channel Skew Measurement
    3. 4.3 Summary and Conclusion
  10. 5Design and Documentation Support
    1. 5.1 Design Support
      1. 5.1.1 Schematics
      2. 5.1.2 Bill of Materials
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4. 5.4 Trademarks
  11. 6About the Authors
    1. 6.1 Acknowledgments
2.3.3.2.2 Radiation-Hardness-Assured (RHA) DC/DC Buck Converter

For supplying accurate power to all 3.3-V devices, a buck converter as pre-regulator is used. This reduces heat generation in the LDOs by reducing the drop voltage. Highly noise-reduced clock generation demands for low-noise power supply and a cascade of buck converter and LDO or set of LDOs is capable of providing this.

Converter Design Specifications:

  • VIN = 5 V
  • VOUT = 3.8 V
  • Ioutmax = 4 A
  • Fsw = 500 kHz
  • RTOP = 10 kΩ, RBOT = 2.64 kΩ
Equation 6. RBOTTOM = VREF / (VOUT – VREF) × RTOP

where

  • VREF = 0.804 V
  • VOUT = 3.8 V
  • RTOP = 10 kΩ
  • RBOTTOM = 2.683 kΩ
  • Std Value = 2.64 kΩ
GUID-20221202-SS0I-3X1W-5N8C-7GJTGSHH7LVJ-low.svg Figure 2-15 Buck Pre-Regulator

The compensation values were determined in WEBENCH® Power Designer and verified via simulation with the average model in TINA-TI.

GUID-20221202-SS0I-H0KB-VFP2-6LMGFBCVRVLP-low.svg Figure 2-16 Simulation Bench for the TPS50601A Buck Regulator

Figure 2-17 illustrates that the resulting phase margin from the simulation was 57.86°.

GUID-20221202-SS0I-FF5Q-8JVJ-T75PQRPCL649-low.svg Figure 2-17 Phase and Gain of TPS50601A With Selected Passives

Use the equations in the section discussing small signal model for frequency compensation from the TPS50601A-SP Radiation Hardened 3-V to 7-V Input, 6-A Synchronous Buck Converter data sheet to recalculate the device loop compensation component values to the desired specifications.