In a JESD204B system environment, data transfer from the JESD204B TX block to the RX block happens in multiframes. These multiframes are aligned to the edges of the local multiframe clock (LMFC), which is internal to the JESD204B RX and TX block. The concept of the LMFC and the associated alignment requirements are critical in applications that require deterministic latency and multiple device synchronization. To achieve deterministic latency, multiple device synchronization, or both is to make sure that the LMFC of each JESD204B device in the JESD204B system environment are aligned. The LMFC for each of the JESD204B devices is aligned through the SYSREF signal, which is globally generated from a common source throughout the JESD204B system. Once the LMFCs of all devices in the system are aligned, the devices are synchronized and data transfer happens at the same rate and at the same instant. Figure 2-2 shows the typical setup for synchronization of multiple JESD204B devices. Such synchronization of the clock sources requires:

1. Phase-align device clocks, sampling clocks (DCLK) at each ADC12DJ3200-SP device
2. In-phase SYSREF to each DCLK to meet SYSREF setup and hold time of the ADCs
3. In-phase FPGA CLK and FPGA SYSREF, if using multiple FPGAs in a system

In this design the ADC12DJ3200-SP is operating in JMODE3 with the highest sampling clock of 3.2 GHz. Based on the ADC12DJ3200-SP data sheet calculation, the required FPGA clock is 160 MHz and the SYSREF frequency is 20 MHz. These are generated by the proposed clocking design TIDA-010191.