TIDUEY8 March   2023

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Design Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 LMK04832-SP
      2. 2.2.2 LMX2615-SP
      3. 2.2.3 CDCLVP111-SP
      4. 2.2.4 ADC12DJ3200QML-SP
    3. 2.3 Design Steps
      1. 2.3.1 Multiple JESD204B Synchronization Requirements
      2. 2.3.2 Clock Tree Design
        1. 2.3.2.1 Clock Frequency Plan
        2. 2.3.2.2 Clock Tree Components
          1. 2.3.2.2.1 Clock Reference
          2. 2.3.2.2.2 Clock Reference Buffer
          3. 2.3.2.2.3 Clock Distribution
          4. 2.3.2.2.4 Frequency Synthesis
        3. 2.3.2.3 Phase Delay Adjustment Options
        4. 2.3.2.4 Phase-Noise Optimization
        5. 2.3.2.5 Single-Event Effects (SEE) Considerations
        6. 2.3.2.6 Expanding Clock Tree for MIMO Systems
      3. 2.3.3 Power Management
        1. 2.3.3.1 Power Design Considerations
        2. 2.3.3.2 Radiation Hardened (Rad-Hard) Power Tree
          1. 2.3.3.2.1 Radiation-Hardness-Assured (RHA) Load-Switches
          2. 2.3.3.2.2 Radiation-Hardness-Assured (RHA) DC/DC Buck Converter
          3. 2.3.3.2.3 Radiation-Hardness-Assured (RHA) Low-Dropout (LDO) Regulators
            1. 2.3.3.2.3.1 3.3-V Linear Regulator
            2. 2.3.3.2.3.2 4.5-V Linear Regulator
        3. 2.3.3.3 Overcurrent Detection Circuit
  8. 3Getting Started Hardware and Software
    1. 3.1 Hardware Configuration
      1. 3.1.1 Clocking Board Setup
        1. 3.1.1.1 Power Supply
        2. 3.1.1.2 Input Reference Signals
        3. 3.1.1.3 Input sync Signal
        4. 3.1.1.4 Output Signals
        5. 3.1.1.5 Programming Interface
        6. 3.1.1.6 FMC+ Adapter Board Setup
        7. 3.1.1.7 ADC12DJ3200 EVM Setup
        8. 3.1.1.8 TSW14J57EVM Setup
        9. 3.1.1.9 Multichannel Synchronization Setup
    2. 3.2 Software
      1. 3.2.1 Software Required
      2. 3.2.2 Clocking Board Programming Sequence
      3. 3.2.3 ADC12DJ3200CVAL EVM Programming Sequence
      4. 3.2.4 TSW14J57EVM Evaluation Programming Sequence
  9. 4Testing and Results
    1. 4.1 Test Setup
    2. 4.2 Results
      1. 4.2.1 Phase Noise Measurement Results
      2. 4.2.2 Multichannel Clock Phase Alignment
      3. 4.2.3 Signal Chain Performance
      4. 4.2.4 Channel-to-Channel Skew Measurement
    3. 4.3 Summary and Conclusion
  10. 5Design and Documentation Support
    1. 5.1 Design Support
      1. 5.1.1 Schematics
      2. 5.1.2 Bill of Materials
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4. 5.4 Trademarks
  11. 6About the Authors
    1. 6.1 Acknowledgments

1 System Description

Phased-array antennas and digital beamforming (DBF) are key technologies with the ability to boost the performance of many satellite applications such as spaceborne radar imaging and broadband satellite communication systems. Digital beamforming unlike analog beamforming, typically requires a set of data converters per antenna element which in turn need precise synchronization. Digital beamforming enables performance improvement and increased flexibility, allowing for new operating modes. One example of this is high-resolution synthetic aperture radar (SAR), a novel radar technique first used in a space-based application by NASA-ISRO in the NISAR project under the name SweepSAR. Beamforming is also a core building block of the 5G mobile broadband universe. In this context, it makes minimal difference whether the 5G transmission is ground-based or spaceborne. Similar to radar applications beamforming in 5G benefits as well from going digital and the clocking requirements are very similar between both application areas.

GUID-20221202-SS0I-MXLN-SFDX-HGMBGDGSSBL6-low.svg Figure 1-1 Clock Subsystem

The focus of this reference design is on the clocking subsystem for the high-speed GSPS JESD204B-enabled ADC12DJ3200QML-SP data converter. The design demonstrates a multichannel, phase-synchronized clocking platform that can be used in applications with precise synchronization requirements across elements. In the minimal form, the design has two high-speed channels for demonstration purposes. Figure 1-1 shows the block diagram of the design. The clock system divides into three main parts: input clock selector and clock reference buffer CDCLVP111-SP, jitter cleaner and clock distribution LMK04832-SP, and sample clock multiplier LMX2615-SP. The heart of the system is the LMK04832-SP. This device removes the jitter from the incoming clock and creates a stable clock framework. The LMK04832-SP also sources the FPGA clocks and the SYSREF signals. For the input clock of the LMX2615-SP clock multiplier, the reference design can be configured to either use a clock output of the LMK04832-SP or an output of the input clock reference buffer CDCLVP111-SP. When the incoming clock has already very-low phase noise, then connecting the LMX2615-SP to the CDCLVP111-SP gives the lowest possible output phase noise for the ADCs. The LMX2615-SP can then take this base clock and use fractional multiplication techniques to generate an up to 15-GHz sampling clock tunable to sub-Hertz accuracy. The system also routes the SYSREF through to the ADC subsystem.

The design features three LMX2615-SP devices but only two of them are used for the technical analysis in this document. Therefore, the diagrams also show only two RF PLL synthesizers. The third LMX2615-SP can, for example, be used as the source for the local oscillator input of a down converter to support higher input frequency bands or other superheterodyne principles.