TIDUEY9 April   2021

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 LP8770
        1. 2.3.1.1 Safety Features
          1. 2.3.1.1.1 Window Watchdog
          2. 2.3.1.1.2 Voltage Monitoring
      2. 2.3.2 AWR1843/xWR6843 mmWave Sensor Solution
    4. 2.4 System Design
      1. 2.4.1 Hardware Block Diagram
      2. 2.4.2 Software Components
        1. 2.4.2.1 Secondary Bootloader (SBL)
        2. 2.4.2.2 mmWaveLink APIs
        3. 2.4.2.3 mmWave Safety Diagnostic Library (SDL)
        4. 2.4.2.4 mmWave SDK Software Block Diagram
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  10. 5About the Author
2.3.1.1.2 Voltage Monitoring

The LP87702-Q1 device has programmable voltage monitoring for the BUCKx and BOOST converter output voltages and for VANA, VMON1 and VMON2 inputs. Monitoring of each signal is independently enabled in PGOOD_CTRL register. Voltage monitoring can be under-voltage monitoring only (PGOOD_WINDOW = 0) or

overvoltage and undervoltage monitoring (PGOOD_WINDOW = 1). This selection is common for all enabled monitoring. Enabled monitoring signals are combined to generate power-good (PG0, PG1) and/or interrupts as described in Power-Good Information to Interrupt and PG0 and PG1 Pins. Monitoring comparators have a dedicated reference and bias block, which is independent of the main reference and bias block.

In the AWR1843Boost EVM, the LP87702-Q1 handles the Voltage monitoring and has capability to enable the watchdog.

  • There are 2 Voltage monitors in LP8770. These are used to monitor 1.24-V rail and 1.8-V rail after the LC filter.
  • The 1.0V derived from LDO (TPS7A53) whose input is 1.24-V is monitored using GPADC in AWR.
  • WDI pin of the LP87702-Q1 is connected to a GPIO(x) of the AWR and this GPIO is used to feed the watchdog at appropriate intervals by the application software.
  • The WD_RESET + PowerGood +GPIO0 pin of the LP87702-Q1 is connected to NRST of the AWR1843.
  • The NERROR of the AWR1843 should be connected to the Reset of the CAN Transceiver.
  • GPADC of the AWR1843 can be used to monitor the 1-V Power rail.

Watch needs to be enabled by writing into the WatchDog register in LP87702Q1 via I2C. For the watchdog operation the application firmware needs to generate a pulse every Window period on the GPIO(x). The recommended way to generate a pulse is to time the application and generate a pulse at appropriate points from the application in AWR1843. We do not recommend to use any timers in 1843 to generate this watchdog pulse.