As shown in the architecture overview, the main switching device needs to support only half the full switching voltage. To support the 800-V DC link voltage of this design, use 600-V rated devices. The switches Q1, Q5, Q4, and Q6 are high-frequency switching and hence must be GaN devices. However, the switches Q2 and Q3 are only switching at 100 Hz and 120 Hz and can use Si MOSFETs.

Conduction loss is mainly determined by the R_DS(on) of the GaN MOSFET and the R_DS(on) of the Si MOSFET. At any instance, there are two devices conducting at the same time (one each of the GaN device and the Si device). So the R_DS(on) of these should be selected based on the conduction loss that can be allowed on them.

Switching loss is a function of the switching frequency and switching energy of each switching element; the switching energy being related to the device current and voltage at the switching transient. Using the switching energy curve in the data sheet, the total switching loss can be estimated. Note that in inverter configuration, only Q1 or Q4 experience switching loss, as Q5 and Q6 work as synchronous switches only and hence experience zero voltage switching. However, since Q5 and Q6 body diodes conduct during dead-time, they can have forward drop loss and reverse recovery loss. However, TI’s GaN devices do not have reverse recovery loss at all and SiC devices have only negligible reverse recovery. Q2 and Q3 switch only at a very low frequency and hence their switching loss can be neglected.

The conduction loss and switching loss can be estimated for all the devices and efficiency can be estimated as explained. With the thermal impedance information of the thermal system design, the proper device rating can be selected. 600-V, 30-mΩ GaN and 650-V, 40-mΩ Si MOSFET are good tradeoffs among thermal, efficiency and cost.