TIDUF08 January   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 General Layout Recommendations
      1. 2.3.1 DLPC3436 Layout Guidelines
        1. 2.3.1.1 PLL Power Layout
        2. 2.3.1.2 I2C Interface Performance
        3. 2.3.1.3 DMD Control and Sub-LVDS Signals
        4. 2.3.1.4 Layout Layer Changes
        5. 2.3.1.5 Stubs
        6. 2.3.1.6 Terminations
        7. 2.3.1.7 Routing Vias
      2. 2.3.2 FPGA DDR2 SDRAM Interface Routing
      3. 2.3.3 DLPA2005 Layout Recommendations
        1. 2.3.3.1 Layout Guidelines
        2. 2.3.3.2 Layout Example
        3. 2.3.3.3 Thermal Considerations
      4. 2.3.4 DMD Flex Cable Interface Layout Guidelines
    4. 2.4 Highlighted Products
  9. 3Hardware
    1. 3.1 Hardware Requirements
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Layout Files
      4. 4.1.4 Mechanical Files
    2. 4.2 Software and FPGA code
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks

2.3.1.3 DMD Control and Sub-LVDS Signals

Table 2-2 Maximum Pin-to-Pin PCB Interconnect Recommendations
DMD BUS SIGNAL(1)(2) SIGNAL INTERCONNECT TOPOLOGY UNIT
SINGLE-BOARD SIGNAL ROUTING LENGTH MULTI-BOARD SIGNAL ROUTING LENGTH
DMD_HS_CLK_P
DMD_HS_CLK_N		 6.0
(152.4)		 See (3) in
(mm)
DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N		 6.0
(152.4)		 See (3) in
(mm)
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
DMD_LS_CLK 6.5
(165.1)		 See (3) in
(mm)
DMD_LS_WDATA 6.5
(165.1)		 See (3) in
(mm)
DMD_LS_RDATA 6.5
(165.1)		 See (3) in
(mm)
DMD_DEN_ARSTZ 7.0
(177.8)		 See (3) in
(mm)
(1) Maximum signal routing length includes escape routing.
(2) Multi-board DMD routing length is more restricted due to the impact of the connector.
(3) Due to PCB variations, these recommendations cannot be defined. The best practice is for any board design to SPICE simulate with the controller IBIS model (found under the Tools & Software tab of the controller web page) to make sure routing lengths do not violate signal requirements.
Table 2-3 High-Speed PCB Signal Routing Matching Requirements
SIGNAL GROUP LENGTH MATCHING(1)(2)(3)
INTERFACE SIGNAL GROUP REFERENCE SIGNAL MAX MISMATCH(4) UNIT
DMD(5) DMD_HS_WDATA_A_P
DMD_HS_WDATA_A_N		 DMD_HS_CLK_P
DMD_HS_CLK_N		 ±1.0
(±25.4)		 in
(mm)
DMD_HS_WDATA_B_P
DMD_HS_WDATA_B_N
DMD_HS_WDATA_C_P
DMD_HS_WDATA_C_N
DMD_HS_WDATA_D_P
DMD_HS_WDATA_D_N
DMD_HS_WDATA_E_P
DMD_HS_WDATA_E_N
DMD_HS_WDATA_F_P
DMD_HS_WDATA_F_N
DMD_HS_WDATA_G_P
DMD_HS_WDATA_G_N
DMD_HS_WDATA_H_P
DMD_HS_WDATA_H_N
DMD DMD_HS_WDATA_x_P DMD_HS_WDATA_x_N ±0.025
(±0.635)		 in
(mm)
DMD DMD_HS_CLK_P DMD_HS_CLK_N ±0.025
(±0.635)		 in
(mm)
DMD DMD_LS_WDATA
DMD_LS_RDATA		 DMD_LS_CLK ±0.2
(±5.08)		 in
(mm)
DMD DMD_DEN_ARSTZ N/A N/A in
(mm)
(1) The length matching values apply to PCB routing lengths only. Internal package routing mismatch associated with the DLPC34xx controller or the DMD require no additional consideration.
(2) Training is applied to DMD HS data lines. This is why the defined matching requirements are slightly relaxed compared to the LS data lines.
(3) DMD LS signals are single ended.
(4) Mismatch variance for a signal group is always with respect to the reference signal.
(5) DMD HS data lines are differential, thus these specifications are pair-to-pair.
Table 2-4 Signal Requirements
PARAMETER REFERENCE REQUIREMENT
Source series termination DMD_LS_WDATA Required
DMD_LS_CLK Required
DMD_DEN_ARSTZ Acceptable
DMD_LS_RDATA Required
DMD_HS_WDATA_x_y Not acceptable
DMD_HS_CLK_y Not acceptable
Endpoint termination DMD_LS_WDATA Not acceptable
DMD_LS_CLK Not acceptable
DMD_DEN_ARSTZ Not acceptable
DMD_LS_RDATA Not acceptable
DMD_HS_WDATA_x_y Not acceptable
DMD_HS_CLK_y Not acceptable
PCB impedance DMD_LS_WDATA 68 Ω ±10%
DMD_LS_CLK 68 Ω ±10%
DMD_DEN_ARSTZ 68 Ω ±10%
DMD_LS_RDATA 68 Ω ±10%
DMD_HS_WDATA_x_y 100 Ω ±10%
DMD_HS_CLK_y 100 Ω ±10%
Signal type DMD_LS_WDATA SDR (single data rate) referenced to DMD_LS_DCLK
DMD_LS_CLK SDR referenced to DMD_LS_DCLK
DMD_DEN_ARSTZ SDR
DMD_LS_RDATA SDR referenced to DMD_LS_DLCK
DMD_HS_WDATA_x_y sub-LVDS
DMD_HS_CLK_y sub-LVDS