TIDUF08 January   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 General Layout Recommendations
      1. 2.3.1 DLPC3436 Layout Guidelines
        1. 2.3.1.1 PLL Power Layout
        2. 2.3.1.2 I2C Interface Performance
        3. 2.3.1.3 DMD Control and Sub-LVDS Signals
        4. 2.3.1.4 Layout Layer Changes
        5. 2.3.1.5 Stubs
        6. 2.3.1.6 Terminations
        7. 2.3.1.7 Routing Vias
      2. 2.3.2 FPGA DDR2 SDRAM Interface Routing
      3. 2.3.3 DLPA2005 Layout Recommendations
        1. 2.3.3.1 Layout Guidelines
        2. 2.3.3.2 Layout Example
        3. 2.3.3.3 Thermal Considerations
      4. 2.3.4 DMD Flex Cable Interface Layout Guidelines
    4. 2.4 Highlighted Products
  9. 3Hardware
    1. 3.1 Hardware Requirements
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Layout Files
      4. 4.1.4 Mechanical Files
    2. 4.2 Software and FPGA code
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks

Highlighted Products

This chipset reference design guide draws upon figures and content from several other published documents related to the DLP300S and DLP301S DLP chipsets. For a list of these documents, see Section 4.3