TIDUF08 January   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 General Layout Recommendations
      1. 2.3.1 DLPC3436 Layout Guidelines
        1. 2.3.1.1 PLL Power Layout
        2. 2.3.1.2 I2C Interface Performance
        3. 2.3.1.3 DMD Control and Sub-LVDS Signals
        4. 2.3.1.4 Layout Layer Changes
        5. 2.3.1.5 Stubs
        6. 2.3.1.6 Terminations
        7. 2.3.1.7 Routing Vias
      2. 2.3.2 FPGA DDR2 SDRAM Interface Routing
      3. 2.3.3 DLPA2005 Layout Recommendations
        1. 2.3.3.1 Layout Guidelines
        2. 2.3.3.2 Layout Example
        3. 2.3.3.3 Thermal Considerations
      4. 2.3.4 DMD Flex Cable Interface Layout Guidelines
    4. 2.4 Highlighted Products
  9. 3Hardware
    1. 3.1 Hardware Requirements
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Layout Files
      4. 4.1.4 Mechanical Files
    2. 4.2 Software and FPGA code
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks

2.3.2 FPGA DDR2 SDRAM Interface Routing

The FPGA to DDR2 SDRAM interface is based on a 400-MHz DDR clock rate. The Intel® Cyclone® IV E FPGA (EP4CE15M9C7N) to an Alliance DDR2 SDRAM (AS4C64M8D2-25BIN) interface diagram is shown in Figure 2-3 and the recommended interface layout guidelines are defined in Table 2-5.

GUID-20230209-SS0I-ZQVP-NQBP-GSGZL9D1CKT8-low.png Figure 2-3 FPGA-DDR2 Interface
Table 2-5 Recommended FPGA-DDR2 PCB Matching and Trace Delays
GROUP GROUP NAME LENGTH MATCH WITHIN GROUP LENGTH MATCH TO OTHER SIGNALS ADDITIONAL ROUTING REQUIREMENTS
MEM_ADDR[13:0], MEM_BA[2:0], MEM_CASn, MEM_RASn, MEM_WEn, MEM_ODT MEM_CKE, MEM_CSn Addr/Cntl Group WITHIN GROUP ±50 ps 0 ps to 15 ps less than MEM_CLK and MEM_CLK_N 50 Ω - place termination at DDR2 end of trace - maximum length 250 ps - minimum length 200 ps
MEM_DQ[7:0], MEM_DM, MEM_DQS Data Group WITHIN GROUP ±10 ps MEM_CLK, MEM_CLK_N ±10 ps 50 Ω - use inner layer - route on same layer - place termination at FPGA end of trace - max length 250 ps - min length 200 ps
MEM_CLK, MEM_CLK_N CLK Group WITHIN GROUP ±2 ps MEM_DQS ±2 ps Must be 0 ps to 15 ps longer than ADDR & CNTL Group 100 differential - minimize trace on outer layer - use inner layer - max length 250 ps - min length 200 ps

PCB routing best practices:

  • Use inner PCB layers when possible
  • Route DDR_DQ(7:0), MEM_DM and DDR_DQS on the same layers