TIDUF12 December   2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 Devices
        1. 2.3.1.1 AWR2243
        2. 2.3.1.2 AM2732R
        3. 2.3.1.3 LP876242-Q1
        4. 2.3.1.4 LM62460-Q1
        5. 2.3.1.5 TCAN1043A-Q1
        6. 2.3.1.6 TCAN1044A-Q1
        7. 2.3.1.7 DP83TC812-Q1
        8. 2.3.1.8 TPS61379-Q1
        9. 2.3.1.9 TMP102-Q1
  8. 3System Design Theory
  9. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Test Setup
      1. 4.2.1 Virtual Antenna Array
    3. 4.3 Test Results
      1. 4.3.1 Angle Resolution Measurement
  10. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout Recommendations
        1. 5.1.3.1 20 GHz (FMCW) RF LO Sync
        2. 5.1.3.2 PCB Layer Stackup
        3. 5.1.3.3 Board Photos
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks

20 GHz (FMCW) RF LO Sync

This reference design is based on TI’s AWR2243 radar chip. Using the 20 GHz LO input and output paths, two of these chips are cascaded together and operated synchronously. This requires that the RF LO frequencies of each chip be synchronized. The AWR2243 synthesizer generates LO between 19 GHz and 20.25 GHz, depending on the programmed chirp RF output frequencies.

The AWR2243 that is designated as the primary, generates a common Local Oscillator (LO) signal (19 GHz to 20.25 GHz) to be shared across all the transmitters and receivers in the entire cascade system.

The primary AWR2243 is capable of supplying the shared LO signal on two different output pins through two different delay matched amplifiers. Either or both of these signals, FM_CW_CLKOUT and FM_CW_SYNCOUT, can be used as the source of the LO from the primary to the secondary device. To avoid skew between the LO signals used in both devices, the LO signal input into the primary needs to pass through a trace that is length-matched to the trace between the primary and the secondary devices. As shown in Figure 5-2, one LO signal output is routed with a trace between devices. Then, the other output LO signal from the primary device is looped back to the LO signal input on the primary device using a trace that is the same length.

GUID-20221118-SS0I-F3X9-XJVR-ZD7ZBWF5LMK6-low.png Figure 5-1 LO Clock Signals
GUID-20221117-SS0I-RMR7-BSHW-LKTZSCQGXWKZ-low.png Figure 5-2 LO Clock Routing