TIDUF13 November   2022 ADS117L11 , ADS127L11

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specification
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Signal-Chain Voltage Levels
        1.       12
      2. 2.2.2 ADC Configuration
      3. 2.2.3 ADC Clocking and Synchronization
      4. 2.2.4 Differential Low-Pass Filter
      5. 2.2.5 Current Source
      6. 2.2.6 Gain Stage and High-Pass Filter
    3. 2.3 Highlighted Products
      1. 2.3.1 ADS127L11
      2. 2.3.2 THS4551
  8. 3System Design Theory
    1. 3.1 IEPE Sensor
      1. 3.1.1 IEPE Sensor Parameters
        1. 3.1.1.1 Sensitivity and Measurement Range
        2. 3.1.1.2 Excitation, Output Bias Voltage, and Output Impedance
        3. 3.1.1.3 Linearity and Temperature Variance
        4. 3.1.1.4 Frequency Response
        5. 3.1.1.5 Noise and Dynamic Range
  9. 4Hardware, Software, Testing, and Test Results
    1. 4.1 Hardware Description
      1. 4.1.1 Board Interface
      2. 4.1.2 Power Configuration
        1. 4.1.2.1 Power Sequence
        2. 4.1.2.2 Analog Supply
        3. 4.1.2.3 Digital Supply
        4. 4.1.2.4 Excitation Current Supply
        5. 4.1.2.5 SPI Connectivity Modes and Their Assembly Variants
          1. 4.1.2.5.1 Daisy-Chain Mode
          2. 4.1.2.5.2 Parallel SDO Mode
          3. 4.1.2.5.3 Parallel SDI Mode and Parallel SDO Mode
          4. 4.1.2.5.4 Clocking Modes
    2. 4.2 Software Requirements
    3. 4.3 Test Setup and Procedure
      1. 4.3.1 Noise Floor and SNR
      2. 4.3.2 Gain and Input Range
      3. 4.3.3 Crosstalk
      4. 4.3.4 Total Harmonic Distortion
      5. 4.3.5 Clock Image Rejection
      6. 4.3.6 Synchronization of the ADCs
      7. 4.3.7 Fault Detection Circuit
    4. 4.4 Test Results
      1. 4.4.1 Noise Floor and Dynamic Range
      2. 4.4.2 Gain and Input Range
      3. 4.4.3 Crosstalk
      4. 4.4.4 Total Harmonic Distortion
      5. 4.4.5 Clock Image Rejection
      6. 4.4.6 Synchronization of the ADCs
      7. 4.4.7 Fault Detection Circuit
      8. 4.4.8 Test With Actual IEPE Sensor
      9. 4.4.9 Measurement Results Summary
  10. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  11. 6About the Author

4.1.1 Board Interface

Figure 4-2 shows various connectors and jumpers used to interface with the design PCB.

GUID-20220829-SS0I-DG8J-KRQ8-VXSRKRXQZKQR-low.png Figure 4-2 PCB Interface
Table 4-1 Board Connectors and Headers
CONNECTOR DESCRIPTION
J9A…J9D Ch1 to Ch4 sensor input (BNC connector, with shield grounded)
J8A…J8D Ch1 to Ch4 excitation current source selector

Short (3,2) top and middle, to use onboard current source (make sure it is powered)

Connect external current source (2,1) middle and bottom, to use external current source

Leave open to evaluate the channel without excitation current (no sensor is connected)
J10A…J10D Ch1 to Ch4 coupling selection

Short: DC coupling, use for Ch4 in case of DC coupling, other channels for testing

Open: AC coupling, default configuration
J5 QHS connector connect to PHI, best practice is to power the board before connection
J2 SPI signals header, use for debugging and probing, or to connect to another board (if no QHS)
J14 DAC and SR signals header, use for driving (no QHS) or monitoring auxiliary signals
J7 nRDY signal header, use for checking the synchronization between ADCs
J15 SMA connector for Clk, based on the assembly can be used either as clock input (crystal is removed), or as a clock output
JP1 Used for EEPROM programming if needed. Not used for the PHI board
J12 External supply for excitation current, if used, make sure J11 is open, D3 indicates active supply
J11 Short to use onboard booster supply for excitation current, make sure J12 is open
J3 Input supply for onboard booster stage, valid input range is 1.8 V to 5.5 V, typically use 5.2 V
J1 Input supply for onboard LDO generating 5 V, valid input range is 5.2 V to 6 V, use 5.2 V
J4 External digital supply, recommended to use 2.5 V. When used make sure J6 is open and that the MCU or controller connected is 2.5-V compatible.
J6 Short to use PHI digital supply (make sure 2.5 V, and J4 is open), open if external supply is to be used
J13 DAC connection short (1,2, right) to use ADC CM (2.5 V) as input attenuator common-mode short (2,3, left) to use DAC as common-mode source for the attenuator use pin1 to monitor ADC CM, pin3 to monitor, use DAC output, pin2 to connect external source
JP3 Control connection for variable current source, connect J13, pin3 to use the DAC
JP2 Supply connection for the variable current source (note ground sign)
JP4 Output connection for variable current source, connect to J8x(1,2) to use as channel ISOURCE