TIDUF13 November 2022 ADS117L11 , ADS127L11
As mentioned in the previous section, a 4-V reference is to be used with the ADS127L11 to maximize the dynamic range. A 16-MHz oscillator clock is also selected as clock reference to the ADC as well as an SPI clock. The ADC can run with clocks up to 25 MHz.
To get the best performance out of the signal-chain, the ADS127L11 ADC has to be configured properly. The following list shows the required settings:
The ADC can be used either in daisy chain or in parallel SDO modes. Equation 1 shows the maximum data rate for daisy-chain mode.
For a 16-MHz SPI clock, 4 devices, and 32b per frame, the maximum data rate is 125 kSPS. To get the output data rate to 125 kSPS, set the OSR=64.
For parallel SDO mode and using the wideband filter, the data rate can be set to a maximum of 400 kSPS. With a 16-MHz clock, only OSR = 64 is possible, and that gives an output data rate of 250 kSPS. To achieve 400 kSPS, replace the onboard 16-MHz oscillator with a 25-MHz oscillator.
For more details about the daisy-chain and parallel connections, see the ADS127L11 400-kSPS, Wide-Bandwidth, 24-Bit, Delta-Sigma ADC data sheet and ADS127L11 in Simultaneous-Sampling Systems application brief.