TIDUF14 October   2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 BQ76952
      2. 2.3.2 LM5163
      3. 2.3.3 MSP430FR2155
      4. 2.3.4 ISO1042
      5. 2.3.5 TPS54308
      6. 2.3.6 ISO7731
      7. 2.3.7 THVD1400
      8. 2.3.8 UCC27524
      9. 2.3.9 TMP61
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Cell Voltage Accuracy
      2. 3.3.2 Pack Current Accuracy
      3. 3.3.3 Auxiliary Power and System Current Consumption
      4. 3.3.4 Cell Balancing
      5. 3.3.5 Protection
      6. 3.3.6 Working Modes Transition
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  10. 5About the Author

3.3.4 Cell Balancing

The design board supports external cell balancing with 16 NPN transistors. The peak balancing current is about 100 mA with 3.5-V cell voltage. This design only balances non-adjacent cells in use. The conditions that trigger cell balancing include: minimum cell voltage is larger than 3300 mV, maximum cell voltage gap is larger than 40 mV, and cell temperature is between –20°C to 60°C. Figure 3-7 shows cell balancing in normal mode. This design also supports cell balancing when no charging or discharging is occurring. Figure 3-8 shows the cell balancing in standby mode.

Figure 3-7 Cell Balancing in Normal Mode
Figure 3-8 Cell Balancing in Standby Mode

More cell balancing analysis is found in the Cell Balancing With BQ769x2 Battery Monitors application note.